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path: root/drivers/clk/ingenic/cgu.h
AgeCommit message (Expand)Author
2022-10-27clk: ingenic: Add .set_rate_hook() for PLL clocksAidan MacDonald
2022-10-27clk: ingenic: Make PLL clock enable_bit and stable_bit optionalAidan MacDonald
2022-10-27clk: ingenic: Make PLL clock "od" field optionalAidan MacDonald
2022-05-18clk: ingenic: Allow specifying common clock flagsAidan MacDonald
2021-06-27clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil
2021-06-27clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil
2021-06-27clk: Support bypassing dividersPaul Cercueil
2020-05-28clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2019-06-25clk: ingenic: Add missing header in cgu.hPaul Cercueil
2019-06-07clk: ingenic: Add support for divider tablesPaul Cercueil
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner
2019-02-22clk: ingenic: Fix doc of ingenic_cgu_div_infoPaul Cercueil
2018-06-15docs: Fix some broken referencesMauro Carvalho Chehab
2018-06-01clk: ingenic: Support specifying "wait for clock stable" delayPaul Cercueil
2018-06-01clk: ingenic: Add support for clocks whose gate bit is invertedPaul Cercueil
2018-01-18clk: ingenic: support PLLs with no bypass bitPaul Cercueil
2018-01-18clk: ingenic: Use const pointer to clk_ops in structPaul Cercueil
2017-11-03Update MIPS email addressesPaul Burton
2016-05-12clk: ingenic: Allow divider value to be dividedHarvey Hunt
2015-06-21clk: ingenic: add driver for Ingenic SoC CGU clocksPaul Burton