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path: root/drivers/clk/ingenic
AgeCommit message (Expand)Author
2023-06-08clk: ingenic: tcu: Switch to determine_rateMaxime Ripard
2023-06-08clk: ingenic: cgu: Switch to determine_rateMaxime Ripard
2023-01-25clk: ingenic: jz4760: Update M/N/OD calculation algorithmPaul Cercueil
2022-11-01clk: Add Ingenic JZ4755 CGU driverSiarhei Volkau
2022-10-27clk: ingenic: Minor cosmetic fixups for X1000Aidan MacDonald
2022-10-27clk: ingenic: Add X1000 audio clocksAidan MacDonald
2022-10-27clk: ingenic: Add .set_rate_hook() for PLL clocksAidan MacDonald
2022-10-27clk: ingenic: Make PLL clock enable_bit and stable_bit optionalAidan MacDonald
2022-10-27clk: ingenic: Make PLL clock "od" field optionalAidan MacDonald
2022-08-31clk: ingenic-tcu: Properly enable registers before accessing timersAidan MacDonald
2022-05-18clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCsAidan MacDonald
2022-05-18clk: ingenic: Mark critical clocks in Ingenic SoCsAidan MacDonald
2022-05-18clk: ingenic: Allow specifying common clock flagsAidan MacDonald
2022-02-17clk: jz4725b: fix mmc0 clock gatingSiarhei Volkau
2022-01-06clk: ingenic: Add MDMA and BDMA clocksPaul Cercueil
2021-11-14Merge tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux...Linus Torvalds
2021-11-11dt-bindings: Rename Ingenic CGU headers to ingenic,*.hPaul Cercueil
2021-11-02clk: ingenic: Fix bugs with divided dividersPaul Cercueil
2021-06-27clk: ingenic: Add support for the JZ4760Paul Cercueil
2021-06-27clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil
2021-06-27clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil
2021-06-27clk: ingenic: Read bypass register only when there is onePaul Cercueil
2021-06-27clk: Support bypassing dividersPaul Cercueil
2020-12-19clk: ingenic: Fix divider calculation with div tablesPaul Cercueil
2020-10-13clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_ratePaul Cercueil
2020-10-13clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENTPaul Cercueil
2020-10-13clk: ingenic: Don't use CLK_SET_RATE_GATE for PLLPaul Cercueil
2020-10-13clk: ingenic: Use readl_poll_timeout instead of custom loopPaul Cercueil
2020-10-13clk: ingenic: Use to_clk_info() macro for all clocksPaul Cercueil
2020-07-27clk: X1000: Add support for calculat REFCLK of USB PHY.周琰杰 (Zhou Yanjie)
2020-07-27clk: JZ4780: Reformat the code to align it.周琰杰 (Zhou Yanjie)
2020-07-27clk: JZ4780: Add functions for enable and disable USB PHY.周琰杰 (Zhou Yanjie)
2020-07-27clk: Ingenic: Add RTC related clocks for Ingenic SoCs.周琰杰 (Zhou Yanjie)
2020-05-28clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unusedStephen Boyd
2020-05-28clk: X1000: Add FIXDIV for SSI clock of X1000.周琰杰 (Zhou Yanjie)
2020-05-28clk: Ingenic: Add CGU driver for X1830.周琰杰 (Zhou Yanjie)
2020-05-28clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)
2020-05-28clk: Ingenic: Remove unnecessary spinlock when reading registers.周琰杰 (Zhou Yanjie)
2020-03-20clk: ingenic/TCU: Fix round_rate returning errorPaul Cercueil
2020-03-20clk: ingenic/jz4770: Exit with error if CGU init failedPaul Cercueil
2020-03-20clk: JZ4780: Add function for enable the second core.周琰杰 (Zhou Yanjie)
2020-03-20clk: Ingenic: Add support for TCU of X1000.周琰杰 (Zhou Yanjie)
2019-11-27Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ...Stephen Boyd
2019-11-22clk: ingenic: Allow drivers to be built with COMPILE_TESTStephen Boyd
2019-11-13clk: Ingenic: Add CGU driver for X1000.Zhou Yanjie
2019-11-08drivers/clk: convert VL struct to struct_sizeStephen Kitt
2019-09-22Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds
2019-08-12clk: ingenic: Use CLK_OF_DECLARE_DRIVER macroPaul Cercueil
2019-08-08clk: jz4740: Add TCU clockPaul Cercueil
2019-08-08clk: ingenic: Add driver for the TCU clocksPaul Cercueil