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path: root/drivers/clk/mediatek/clk-pll.c
AgeCommit message (Expand)Author
2024-01-03clk: mediatek: add pcw_chg_bit control for PLLs of MT7988Sam Shih
2023-10-24clk: mediatek: fix double free in mtk_clk_register_pllfh()Dan Carpenter
2022-11-29clk: mediatek: Export PLL operations symbolsJohnson Wang
2022-05-19clk: mediatek: Switch to clk_hw provider APIsChen-Yu Tsai
2022-05-19clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai
2022-05-18clk: mediatek: use en_mask as a pure div_en_maskChun-Jie Chen
2022-02-17clk: mediatek: Warn if clk IDs are duplicatedChen-Yu Tsai
2022-02-17clk: mediatek: pll: Implement error handling in register APIChen-Yu Tsai
2022-02-17clk: mediatek: pll: Clean up included headersChen-Yu Tsai
2022-02-17clk: mediatek: pll: Implement unregister APIChen-Yu Tsai
2022-02-17clk: mediatek: pll: Split definitions into separate header fileChen-Yu Tsai
2022-02-17clk: mediatek: Use %pe to print errorsChen-Yu Tsai
2021-09-14clk: mediatek: support COMMON_CLK_MEDIATEK module buildMiles Chen
2021-09-14clk: mediatek: Fix corner case of tuner_en_regChun-Jie Chen
2021-07-27clk: mediatek: Add configurable enable control to mtk_pll_dataChun-Jie Chen
2021-07-27clk: mediatek: Fix asymmetrical PLL enable and disable controlChun-Jie Chen
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner
2019-04-11clk: mediatek: Allow changing PLL rate when it is offJames Liao
2019-04-11clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_dataWeiyi Lu
2019-04-11clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_dataOwen Chen
2019-04-11clk: mediatek: Disable tuner_en before change PLL rateOwen Chen
2017-11-02clk: mediatek: add the option for determining PLL source clockChen Zhong
2017-11-02clk: mediatek: Add MT2712 clock supportweiyi.lu@mediatek.com
2016-11-08clk: mediatek: Add MT2701 clock supportShunli Wang
2016-08-18clk: mediatek: remove __init from clk registration functionsJames Liao
2015-10-01clk: mediatek: Add USB clock support in MT8173 APMIXEDSYSJames Liao
2015-07-28clk: mediatek: Add MT8173 MMPLL change rate supportJames Liao
2015-07-28clk: mediatek: Fix calculation of PLL rate settingsJames Liao
2015-07-28clk: mediatek: Fix PLL registers setting flowJames Liao
2015-05-19clk: mediatek: Initialize clk_init_dataRicky Liang
2015-05-05clk: mediatek: Add initial common clock support for Mediatek SoCs.James Liao
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