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path: root/drivers/clk/mmp/clk-of-pxa168.c
AgeCommit message (Expand)Author
2022-09-30clk: mmp: pxa168: control shared SDH bits with separate clockDoug Brown
2022-09-30clk: mmp: pxa168: add clocks for SDH2 and SDH3Doug Brown
2022-09-30clk: mmp: pxa168: fix GPIO clock enable bitsDoug Brown
2022-09-30clk: mmp: pxa168: add muxes for more peripheralsDoug Brown
2022-09-30clk: mmp: pxa168: fix incorrect parent clocksDoug Brown
2022-09-30clk: mmp: pxa168: fix const-correctnessDoug Brown
2022-09-30clk: mmp: pxa168: add new clocks for peripheralsDoug Brown
2022-09-30clk: mmp: pxa168: fix incorrect dividersDoug Brown
2022-09-30clk: mmp: pxa168: add additional register definesDoug Brown
2022-06-10treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (pa...Thomas Gleixner
2016-11-01clk: mmp: pxa168: fix return value check in pxa168_clk_init()Wei Yongjun
2016-04-15clk: mmp: Remove CLK_IS_ROOTStephen Boyd
2015-06-04clk: mmp: add timer clock for pxa168/mmp2/pxa910Chao Xie
2015-06-04clk: mmp: add fixed clock UBS_PLL for pxa910/pxa168Chao Xie
2014-11-12clk: mmp: add pxa168 DT support for clock driverChao Xie