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path: root/drivers/clk/rockchip/clk-rk3568.c
AgeCommit message (Expand)Author
2024-05-04clk: rockchip: rk3568: Add PLL rate for 724 MHzLucas Stach
2024-04-10clk: rockchip: rk3568: Add missing USB480M_PHY muxDavid Jander
2024-01-25clk: rockchip: rk3568: Add PLL rate for 128MHzChris Morgan
2024-01-12Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2023-12-05clk: rockchip: rk3568: Mark pclk_usb as criticalChris Morgan
2023-12-05clk: rockchip: rk3568: Add PLL rate for 126.4MHzChris Morgan
2023-11-16clk: rockchip: rk3568: Add PLL rate for 292.5MHzChris Morgan
2023-11-16clk: rockchip: rk3568: Add PLL rate for 115.2MHzChris Morgan
2023-08-30Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...Stephen Boyd
2023-07-19clk: Explicitly include correct DT includesRob Herring
2023-07-10clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHzAlibek Omarov
2023-07-10clk: rockchip: rk3568: Add PLL rate for 101MHzAlibek Omarov
2022-05-03clk: rockchip: Mark hclk_vo as critical on rk3568Sascha Hauer
2022-02-23clk/rockchip: Use of_device_get_match_data()Minghao Chi (CGEL ZTE)
2022-02-08clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568Sascha Hauer
2022-02-08clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568Sascha Hauer
2022-02-08clk: rockchip: Add more PLL rates for rk3568Sascha Hauer
2021-11-02clk: rockchip: drop module parts from rk3399 and rk3568 driversHeiko Stuebner
2021-11-02Revert "clk: rockchip: use module_platform_driver_probe"Heiko Stuebner
2021-09-21clk: rockchip: use module_platform_driver_probeMiles Chen
2021-05-24clk: rockchip: fix rk3568 cpll clk gate bitsPeter Geis
2021-03-21clk: rockchip: add clock controller for rk3568Elaine Zhang