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2021-02-26Merge tag 'riscv-for-linus-5.12-mw0' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: "A handful of new RISC-V related patches for this merge window: - A check to ensure drivers are properly using uaccess. This isn't manifesting with any of the drivers I'm currently using, but may catch errors in new drivers. - Some preliminary support for the FU740, along with the HiFive Unleashed it will appear on. - NUMA support for RISC-V, which involves making the arm64 code generic. - Support for kasan on the vmalloc region. - A handful of new drivers for the Kendryte K210, along with the DT plumbing required to boot on a handful of K210-based boards. - Support for allocating ASIDs. - Preliminary support for kernels larger than 128MiB. - Various other improvements to our KASAN support, including the utilization of huge pages when allocating the KASAN regions. We may have already found a bug with the KASAN_VMALLOC code, but it's passing my tests. There's a fix in the works, but that will probably miss the merge window. * tag 'riscv-for-linus-5.12-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (75 commits) riscv: Improve kasan population by using hugepages when possible riscv: Improve kasan population function riscv: Use KASAN_SHADOW_INIT define for kasan memory initialization riscv: Improve kasan definitions riscv: Get rid of MAX_EARLY_MAPPING_SIZE soc: canaan: Sort the Makefile alphabetically riscv: Disable KSAN_SANITIZE for vDSO riscv: Remove unnecessary declaration riscv: Add Canaan Kendryte K210 SD card defconfig riscv: Update Canaan Kendryte K210 defconfig riscv: Add Kendryte KD233 board device tree riscv: Add SiPeed MAIXDUINO board device tree riscv: Add SiPeed MAIX GO board device tree riscv: Add SiPeed MAIX DOCK board device tree riscv: Add SiPeed MAIX BiT board device tree riscv: Update Canaan Kendryte K210 device tree dt-bindings: add resets property to dw-apb-timer dt-bindings: fix sifive gpio properties dt-bindings: update sifive uart compatible string dt-bindings: update sifive clint compatible string ...
2021-02-24Merge tag 'driver-core-5.12-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core / debugfs update from Greg KH: "Here is the "big" driver core and debugfs update for 5.12-rc1 This set of driver core patches caused a bunch of problems in linux-next for the past few weeks, when Saravana tried to set fw_devlink=on as the default functionality. This caused a number of systems to stop booting, and lots of bugs were fixed in this area for almost all of the reported systems, but this option is not ready to be turned on just yet for the default operation based on this testing, so I've reverted that change at the very end so we don't have to worry about regressions in 5.12 We will try to turn this on for 5.13 if testing goes better over the next few months. Other than the fixes caused by the fw_devlink testing in here, there's not much more: - debugfs fixes for invalid input into debugfs_lookup() - kerneldoc cleanups - warn message if platform drivers return an error on their remove callback (a futile effort, but good to catch). All of these have been in linux-next for a while now, and the regressions have gone away with the revert of the fw_devlink change" * tag 'driver-core-5.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (35 commits) Revert "driver core: Set fw_devlink=on by default" of: property: fw_devlink: Ignore interrupts property for some configs debugfs: do not attempt to create a new file before the filesystem is initalized debugfs: be more robust at handling improper input in debugfs_lookup() driver core: auxiliary bus: Fix calling stage for auxiliary bus init of: irq: Fix the return value for of_irq_parse_one() stub of: irq: make a stub for of_irq_parse_one() clk: Mark fwnodes when their clock provider is added/removed PM: domains: Mark fwnodes when their powerdomain is added/removed irqdomain: Mark fwnodes when their irqdomain is added/removed driver core: fw_devlink: Handle suppliers that don't use driver core of: property: Add fw_devlink support for optional properties driver core: Add fw_devlink.strict kernel param of: property: Don't add links to absent suppliers driver core: fw_devlink: Detect supplier devices that will never be added driver core: platform: Emit a warning if a remove callback returned non-zero of: property: Fix fw_devlink handling of interrupts/interrupts-extended gpiolib: Don't probe gpio_device if it's not the primary device device.h: Remove bogus "the" in kerneldoc gpiolib: Bind gpio_device to a driver to enable fw_devlink=on by default ...
2021-02-22clk: Add RISC-V Canaan Kendryte K210 clock driverDamien Le Moal
Add a clock provider driver for the Canaan Kendryte K210 RISC-V SoC. This new driver with the compatible string "canaan,k210-clk" implements support for the full clock structure of the K210 SoC. Since it is required for the correct operation of the SoC, this driver is selected by default for compilation when the SOC_CANAAN option is selected. With this change, the k210-sysctl driver is turned into a simple platform driver which enables its power bus clock and triggers populating its child nodes. The sysctl driver retains the SOC early initialization code, but the implementation now relies on the new function k210_clk_early_init() provided by the new clk-k210 driver. The clock structure implemented and many of the coding ideas for the driver come from the work by Sean Anderson on the K210 support for the U-Boot project. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-02-22Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This is all driver updates, the majority of which is a bunch of new Qualcomm clk drivers that dominate the diffstat because we add support for six SoCs from that particular vendor. The other big change is the removal of various clk drivers that are no longer used now that the kernel is dropping support for those SoCs. Beyond that there's the usual non-critical fixes for existing drivers and a good number of patches from Lee Jones that cleanup a bunch of W=1 enabled builds. Removed Drivers: - Remove efm32 clk driver - Remove tango4 clk driver - Remove zte zx clk driver - Remove sirf prima2/atlast clk drivers - Remove u300 clk driver New Drivers: - PLL support on MStar/SigmaStar ARMv7 SoCs - CPU clks for Qualcomm SDX55 - GCC and RPMh clks for Qualcomm SC8180x and SC7280 SoCs - GCC clks for Qualcomm SM8350 - GPU clks for Qualcomm SDM660/SDM630 Updates: - Video clk fixups on Qualcomm SM8250 - Improvements for multimedia clks on Qualcomm MSM8998 - Fix many warnings with W=1 enabled builds under drivers/clk/ - Support crystal load capacitance for Versaclock VC5 - Add a "skip recall" DT binding for Silicon Labs' si570 to avoid glitches at boot - Convert Xilinx VCU clk driver to a proper clk provider driver - Expose Xilinx ZynqMP clk driver to more platforms - Amlogic pll driver fixup - Amlogic meson8b clock controller dt support clean up - Remove mipi clk from the Amlogic axg clock controller - New Rockchip rk3368 clock ids related to camera input - Use pr_notice() instead of pr_warn() on i.MX6Q pre-boot ldb_di_clk reparenting - A series from Liu Ying that adds some SCU clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems - A series from Lucas Stach that adds PLL monitor clocks for i.MX8MQ, and clkout1/2 support for i.MX8MM/MN - Add I2c and Ethernet (RAVB) clocks on Renesas R-Car V3U - Add timer (TMU) clocks on most Renesas R-Car Gen3 SoCs - Add video-related (FCPVD/VSPD/VSPX), watchdog (RWDT), serial (HSCIF), pincontrol/GPIO (PFC/GPIO), SPI (MSIOF), SDHI, and DMA (SYS-DMAC) clocks on Renesas R-Car V3U - Add support for the USB 2.0 clock selector on Renesas RZ/G2 SoCs - Allwinner H616 SoC clk support" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (171 commits) clk: mstar: msc313-mpll: Fix format specifier clk: mstar: Allow MStar clk drivers to be compile tested clk: qoriq: use macros to generate pll_mask clk: qcom: Add Global Clock controller (GCC) driver for SC7280 dt-bindings: clock: Add SC7280 GCC clock binding clk: qcom: rpmh: Add support for RPMH clocks on SC7280 dt-bindings: clock: Add RPMHCC bindings for SC7280 clk: qcom: gcc-sm8350: add gdsc dt-bindings: clock: Add QCOM SDM630 and SDM660 graphics clock bindings clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driver clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers dt-bindings: clock: Add support for the SDM630 and SDM660 mmcc clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as critical clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as critical clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc clk: qcom: gdsc: Implement NO_RET_PERIPH flag clk: mstar: MStar/SigmaStar MPLL driver ...
2021-02-20Merge tag 'pm-5.12-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull power management updates from Rafael Wysocki: "These add a new power capping facility allowing aggregate power constraints to be applied to sets of devices in a distributed manner, add a new CPU ID to the RAPL power capping driver and improve it, drop a cpufreq driver belonging to a platform that is not supported any more, drop two redundant cpufreq driver flags, update cpufreq drivers (intel_pstate, brcmstb-avs, qcom-hw), update the operating performance points (OPP) framework (code cleanups, new helpers, devfreq-related modifications), clean up devfreq, extend the PM clock layer, update the cpupower utility and make assorted janitorial changes. Specifics: - Add new power capping facility called DTPM (Dynamic Thermal Power Management), based on the existing power capping framework, to allow aggregate power constraints to be applied to sets of devices in a distributed manner, along with a CPU backend driver based on the Energy Model (Daniel Lezcano, Dan Carpenter, Colin Ian King). - Add AlderLake Mobile support to the Intel RAPL power capping driver and make it use the topology interface when laying out the system topology (Zhang Rui, Yunfeng Ye). - Drop the cpufreq tango driver belonging to a platform that is not supported any more (Arnd Bergmann). - Drop the redundant CPUFREQ_STICKY and CPUFREQ_PM_NO_WARN cpufreq driver flags (Viresh Kumar). - Update cpufreq drivers: * Fix max CPU frequency discovery in the intel_pstate driver and make janitorial changes in it (Chen Yu, Rafael Wysocki, Nigel Christian). * Fix resource leaks in the brcmstb-avs-cpufreq driver (Christophe JAILLET). * Make the tegra20 driver use the resource-managed API (Dmitry Osipenko). * Enable boost support in the qcom-hw driver (Shawn Guo). - Update the operating performance points (OPP) framework: * Clean up the OPP core (Dmitry Osipenko, Viresh Kumar). * Extend the OPP API by adding new helpers to it (Dmitry Osipenko, Viresh Kumar). * Allow required OPPs to be used for devfreq devices and update the devfreq governor code accordingly (Saravana Kannan). * Prepare the framework for introducing new dev_pm_opp_set_opp() helper (Viresh Kumar). * Drop dev_pm_opp_set_bw() and update related drivers (Viresh Kumar). * Allow lazy linking of required-OPPs (Viresh Kumar). - Simplify and clean up devfreq somewhat (Lukasz Luba, Yang Li, Pierre Kuo). - Update the generic power domains (genpd) framework: * Use device's next wakeup to determine domain idle state (Lina Iyer). * Improve initialization and debug (Dmitry Osipenko). * Simplify computations (Abaci Team). - Make janitorial changes in the core code handling system sleep and PM-runtime (Bhaskar Chowdhury, Bjorn Helgaas, Rikard Falkeborn, Zqiang). - Update the MAINTAINERS entry for the exynos cpuidle driver and drop DEBUG definition from intel_idle (Krzysztof Kozlowski, Tom Rix). - Extend the PM clock layer to cover clocks that must sleep (Nicolas Pitre). - Update the cpupower utility: * Update cpupower command, add support for AMD family 0x19 and clean up the code to remove many of the family checks to make future family updates easier (Nathan Fontenot, Robert Richter). * Add Makefile dependencies for install targets to allow building cpupower in parallel rather than serially (Ivan Babrou). - Make janitorial changes in power management Kconfig (Lukasz Luba)" * tag 'pm-5.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (89 commits) MAINTAINERS: cpuidle: exynos: include header in file pattern powercap: intel_rapl: Use topology interface in rapl_init_domains() powercap: intel_rapl: Use topology interface in rapl_add_package() PM: sleep: Constify static struct attribute_group PM: Kconfig: remove unneeded "default n" options PM: EM: update Kconfig description and drop "default n" option cpufreq: Remove unused flag CPUFREQ_PM_NO_WARN cpufreq: Remove CPUFREQ_STICKY flag PM / devfreq: Add required OPPs support to passive governor PM / devfreq: Cache OPP table reference in devfreq OPP: Add function to look up required OPP's for a given OPP PM / devfreq: rk3399_dmc: Remove unneeded semicolon opp: Replace ENOTSUPP with EOPNOTSUPP opp: Fix "foo * bar" should be "foo *bar" opp: Don't ignore clk_get() errors other than -ENOENT opp: Update bandwidth requirements based on scaling up/down opp: Allow lazy-linking of required-opps opp: Remove dev_pm_opp_set_bw() devfreq: tegra30: Migrate to dev_pm_opp_set_opp() drm: msm: Migrate to dev_pm_opp_set_opp() ...
2021-02-20Merge tag 'arm-drivers-v5.12' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "Updates for SoC specific drivers include a few subsystems that have their own maintainers but send them through the soc tree: SCMI firmware: - add support for a completion interrupt Reset controllers: - new driver for BCM4908 - new devm_reset_control_get_optional_exclusive_released() function Memory controllers: - Renesas RZ/G2 support - Tegra124 interconnect support - Allow more drivers to be loadable modules TEE/optee firmware: - minor code cleanup The other half of this is SoC specific drivers that do not belong into any other subsystem, most of them living in drivers/soc: - Allwinner/sunxi power management work - Allwinner H616 support - ASpeed AST2600 system identification support - AT91 SAMA7G5 SoC ID driver - AT91 SoC driver cleanups - Broadcom BCM4908 power management bus support - Marvell mbus cleanups - Mediatek MT8167 power domain support - Qualcomm socinfo driver support for PMIC - Qualcomm SoC identification for many more products - TI Keystone driver cleanups for PRUSS and elsewhere" * tag 'arm-drivers-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (89 commits) soc: aspeed: socinfo: Add new systems soc: aspeed: snoop: Add clock control logic memory: tegra186-emc: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE memory: samsung: exynos5422-dmc: Correct function names in kerneldoc memory: ti-emif-pm: Drop of_match_ptr from of_device_id table optee: simplify i2c access drivers: soc: atmel: fix type for same7 tee: optee: remove need_resched() before cond_resched() soc: qcom: ocmem: don't return NULL in of_get_ocmem optee: sync OP-TEE headers tee: optee: fix 'physical' typos drivers: optee: use flexible-array member instead of zero-length array tee: fix some comment typos in header files soc: ti: k3-ringacc: Use of_device_get_match_data() soc: ti: pruss: Refactor the CFG sub-module init soc: mediatek: pm-domains: Don't print an error if child domain is deferred soc: mediatek: pm-domains: Add domain regulator supply dt-bindings: power: Add domain regulator supply soc: mediatek: cmdq: Remove cmdq_pkt_flush() soc: mediatek: pm-domains: Add support for mt8167 ...
2021-02-16Merge branches 'clk-socfpga', 'clk-mstar', 'clk-qcom' and 'clk-warnings' ↵Stephen Boyd
into clk-next - PLL support on MStar/SigmaStar ARMv7 SoCs - CPU clks for Qualcomm SDX55 - GCC and RPMh clks for Qualcomm SC8180x and SC7280 SoCs - GCC clks for Qualcomm SM8350 - Video clk fixups on Qualcomm SM8250 - GPU clks for Qualcomm SDM660/SDM630 - Improvements for multimedia clks on Qualcomm MSM8998 - Fix many warnings with W=1 enabled builds under drivers/clk/ * clk-socfpga: clk: socfpga: agilex: add clock driver for eASIC N5X platform dt-bindings: documentation: add clock bindings information for eASIC N5X * clk-mstar: clk: mstar: msc313-mpll: Fix format specifier clk: mstar: Allow MStar clk drivers to be compile tested clk: mstar: MStar/SigmaStar MPLL driver clk: fixed: add devm helper for clk_hw_register_fixed_factor() dt-bindings: clk: mstar msc313 mpll binding description dt-bindings: clk: mstar msc313 mpll binding header * clk-qcom: (42 commits) clk: qcom: Add Global Clock controller (GCC) driver for SC7280 dt-bindings: clock: Add SC7280 GCC clock binding clk: qcom: rpmh: Add support for RPMH clocks on SC7280 dt-bindings: clock: Add RPMHCC bindings for SC7280 clk: qcom: gcc-sm8350: add gdsc dt-bindings: clock: Add QCOM SDM630 and SDM660 graphics clock bindings clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driver clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers dt-bindings: clock: Add support for the SDM630 and SDM660 mmcc clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as critical clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as critical clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc clk: qcom: gdsc: Implement NO_RET_PERIPH flag clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clks clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as critical ... * clk-warnings: (27 commits) clk: zynq: clkc: Remove various instances of an unused variable 'clk' clk: versatile: clk-icst: Fix worthy struct documentation block clk: ti: gate: Fix possible doc-rot in 'omap36xx_gate_clk_enable_with_hsdiv_restore' clk: ti: dpll: Fix misnaming of '_register_dpll()'s 'user' parameter clk: ti: clockdomain: Fix description for 'omap2_init_clk_clkdm's hw param clk: st: clkgen-fsyn: Fix worthy struct documentation demote partially filled one clk: st: clkgen-pll: Demote unpopulated kernel-doc header clk: mvebu: ap-cpu-clk: Demote non-conformant kernel-doc header clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc' clk: socfpga: clk-pll: Remove unused variable 'rc' clk: sifive: fu540-prci: Declare static const variable 'prci_clk_fu540' where it's used clk: bcm: clk-iproc-pll: Demote kernel-doc abuse clk: zynqmp: divider: Add missing description for 'max_div' clk: spear: Move prototype to accessible header clk: qcom: clk-rpm: Remove a bunch of superfluous code clk: clk-xgene: Add description for 'mask' and fix formatting for 'flags' clk: qcom: mmcc-msm8974: Remove unused static const tables 'mmcc_xo_mmpll0_1_2_gpll0{map}' clk: clk-npcm7xx: Remove unused static const tables 'npcm7xx_gates' and 'npcm7xx_divs_fx' clk: clk-fixed-mmio: Demote obvious kernel-doc abuse clk: qcom: gcc-ipq4019: Remove unused variable 'ret' ...
2021-02-16Merge branches 'clk-vc5', 'clk-silabs', 'clk-aspeed', 'clk-qoriq' and ↵Stephen Boyd
'clk-rohm' into clk-next - Support crystal load capacitance for Versaclock VC5 - Add a "skip recall" DT binding for Silicon Labs' si570 to avoid glitches at boot * clk-vc5: clk: vc5: Add support for optional load capacitance dt-bindings: clk: versaclock5: Add optional load capacitance property * clk-silabs: clk: si570: Skip NVM to RAM recall operation if an optional property is set dt-bindings: clock: si570: Add 'silabs,skip-recall' property * clk-aspeed: clk: aspeed: Fix APLL calculate formula from ast2600-A2 * clk-qoriq: clk: qoriq: use macros to generate pll_mask * clk-rohm: clk: BD718x7: Do not depend on parent driver data
2021-02-16Merge branches 'clk-mediatek', 'clk-imx', 'clk-amlogic' and 'clk-at91' into ↵Stephen Boyd
clk-next * clk-mediatek: clk: mediatek: mux: Update parent at enable time clk: mediatek: mux: Drop unused clock ops clk: mediatek: Select all the MT8183 clocks by default * clk-imx: dt-bindings: clock: imx: Switch to my personal address MAINTAINERS: Add section for NXP i.MX clock drivers clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible header clk: imx8mn: add clkout1/2 support clk: imx8mm: add clkout1/2 support clk: imx8mq: add PLL monitor output clk: imx: clk-imx31: Remove unused static const table 'uart_clks' clk: imx6q: demote warning about pre-boot ldb_di_clk reparenting clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2() clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks * clk-amlogic: clk: meson: axg: Remove MIPI enable clock gate clk: meson-axg: remove CLKID_MIPI_ENABLE dt-bindings: clock: meson8b: remove non-existing clock macros clk: meson: meson8b: remove compatibility code for old .dtbs clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate() clk: meson: clk-pll: make "ret" a signed integer clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL * clk-at91: clk: at91: Fix the declaration of the clocks
2021-02-16Merge branch 'clk-unused' into clk-nextStephen Boyd
- Remove efm32 clk driver - Remove tango4 clk driver - Remove zte zx clk driver - Remove sirf prima2/atlast clk drivers - Remove u300 clk driver * clk-unused: clk: remove u300 driver clk: remove sirf prima2/atlas drivers clk: remove zte zx driver clk: remove tango4 driver clk: Drop unused efm32gg driver
2021-02-16Merge branches 'clk-doc', 'clk-renesas', 'clk-allwinner', 'clk-rockchip' and ↵Stephen Boyd
'clk-xilinx' into clk-next - Convert Xilinx VCU clk driver to a proper clk provider driver - Expose Xilinx ZynqMP clk driver to more platforms * clk-doc: linux/clk.h: use correct kernel-doc notation for 2 functions * clk-renesas: (21 commits) clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentation clk: renesas: r8a779a0: Add RAVB clocks clk: renesas: r8a779a0: Add I2C clocks dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add support for RZ/G2 M/N/H clk: renesas: r8a779a0: Add SYS-DMAC clocks clk: renesas: r8a779a0: Add SDHI support clk: renesas: rcar-gen3: Factor out CPG library clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clock clk: renesas: r8a779a0: Add MSIOF clocks clk: renesas: r8a779a0: Add PFC/GPIO clocks clk: renesas: r8a779a0: Fix parent of CBFUSA clock clk: renesas: r8a779a0: Remove non-existent S2 clock clk: renesas: r8a779a0: Add HSCIF support clk: renesas: r8a779a0: Add RWDT clocks clk: renesas: r8a779a0: Add VSPX clock support clk: renesas: r8a779a0: Add VSPD clock support clk: renesas: r8a779a0: Add FCPVD clock support clk: renesas: r8a77995: Add TMU clocks clk: renesas: r8a77990: Add TMU clocks clk: renesas: r8a77965: Add TMU clocks ... * clk-allwinner: clk: sunxi-ng: Add support for the Allwinner H616 CCU clk: sunxi-ng: Add support for the Allwinner H616 R-CCU dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 clk: sunxi-ng: h6: Fix clock divider range on some clocks clk: sunxi: clk-mod0: Demote non-conformant kernel-doc header clk: sunxi: clk-a10-ve: Demote obvious kernel-doc abuse clk: sunxi: clk-sunxi: Demote a bunch of non-conformant kernel-doc headers clk: sunxi-ng: h6: Fix CEC clock clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and reset * clk-rockchip: clk: rockchip: fix DPHY gate locations on rk3368 clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368 clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368 clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368 clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368 clk: rockchip: Demote non-conformant kernel-doc header in half-divider clk: rockchip: Demote kernel-doc abuses to standard comment blocks in plls clk: rockchip: Remove unused/undocumented struct members from clk-cpu clk: rockchip: Demote non-conformant kernel-doc headers in main clock code * clk-xilinx: clk: xilinx: move xlnx_vcu clock driver from soc soc: xilinx: vcu: fix alignment to open parenthesis soc: xilinx: vcu: fix repeated word the in comment soc: xilinx: vcu: use bitfields for register definition soc: xilinx: vcu: remove calculation of PLL configuration soc: xilinx: vcu: make the PLL configurable soc: xilinx: vcu: make pll post divider explicit soc: xilinx: vcu: implement clock provider for output clocks soc: xilinx: vcu: register PLL as fixed rate clock soc: xilinx: vcu: implement PLL disable soc: xilinx: vcu: add helpers for configuring PLL soc: xilinx: vcu: add helper to wait for PLL locked soc: xilinx: vcu: drop coreclk from struct xlnx_vcu clk: divider: fix initialization with parent_hw ARM: dts: vcu: define indexes for output clocks clk: axi-clkgen: use devm_platform_ioremap_resource() short-hand dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP support clk: clk-axiclkgen: add ZynqMP PFD and VCO limits clk: axi-clkgen: replace ARCH dependencies with driver deps
2021-02-16clk: mstar: msc313-mpll: Fix format specifierDaniel Palmer
The output dividers are unsigned int so the format specifier should have been %u not %d. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Link: https://lore.kernel.org/r/20210215115710.3762276-2-daniel@0x0f.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-16clk: mstar: Allow MStar clk drivers to be compile testedDaniel Palmer
Allow COMPILE_TEST to also build the MStar clk drivers instead of only building them when ARCH_MSTARV7 is selected. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Suggested-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210215115710.3762276-1-daniel@0x0f.com [sboyd@kernel.org: Drop regmap select too] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-15Merge branches 'pm-sleep', 'pm-core', 'pm-domains' and 'pm-clk'Rafael J. Wysocki
* pm-sleep: PM: sleep: Constify static struct attribute_group PM: sleep: Use dev_printk() when possible PM: sleep: No need to check PF_WQ_WORKER in thaw_kernel_threads() * pm-core: PM: runtime: Fix typos and grammar PM: runtime: Fix resposible -> responsible in runtime.c * pm-domains: PM: domains: Simplify the calculation of variables PM: domains: Add "performance" column to debug summary PM: domains: Make of_genpd_add_subdomain() return -EPROBE_DEFER PM: domains: Make set_performance_state() callback optional PM: domains: use device's next wakeup to determine domain idle state PM: domains: inform PM domain of a device's next wakeup * pm-clk: PM: clk: make PM clock layer compatible with clocks that must sleep
2021-02-14clk: qoriq: use macros to generate pll_maskWasim Khan
Use macros to generate pll_mask to make code more readable. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Link: https://lore.kernel.org/r/20210125142513.3919014-1-wasim.khan@oss.nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: Add Global Clock controller (GCC) driver for SC7280Taniya Das
Add support for the global clock controller found on SC7280 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1612981579-17391-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: rpmh: Add support for RPMH clocks on SC7280Taniya Das
Add support for RPMH clocks on SC7280 SoCs. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1612977230-11566-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: gcc-sm8350: add gdscVinod Koul
Add the GDSC found in GCC for SM8350 SoC Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210210161649.431741-1-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driverAngeloGioacchino Del Regno
The GPUCC manages the clocks for the Adreno GPU found on the SDM630, SDM636, SDM660 SoCs. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-9-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3dAngeloGioacchino Del Regno
In the previous commit ("clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers") the gfx3d ping-pong ops (clk_gfx3d_ops) were generalized in order to be able to reuse the same ops for more than just one clock for one SoC: follow the change here in the MSM8996 MMCC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-7-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbersAngeloGioacchino Del Regno
The function clk_gfx3d_determine_rate is selecting different PLLs to manage the GFX3D clock source in a special way: this one needs to be ping-pong'ed on different PLLs to ensure stability during frequency switching (set a PLL rate, let it stabilize, switch the RCG to the new PLL) and fast frequency transitions. This technique is currently being used in the MSM8996 SoC and the function was assuming that the parents were always at a specific index in the parents list, which is TRUE, if we use this only on the MSM8996 MMCC. Unfortunately, MSM8996 is not the only SoC that needs to ping-pong the graphics RCG, so choices are: 1. Make new special ops just to hardcode *again* other indexes, creating code duplication for (imo) no reason; or 2. Generalize this function, so that it becomes usable for a range of SoCs with slightly different ping-pong configuration. In this commit, the second road was taken: define a new "special" struct clk_rcg2_gfx3d, containing the ordered list of parents to ping-pong the graphics clock on, and the "regular" rcg2 clock structure in order to generalize the clk_gfx3d_determine_rate function and make it working for other SoCs. As for the function itself it is left with the assumption that we need to ping-pong over three parents. The reasons for this are: 1. The initial model was MSM8996, which has 3 parents for the graphics clock pingpong; 2. The other example that was taken into consideration is the SDM630/636/660 SoC gpu clock controller, which is ping-ponging over two dynamic clocked and one fixed clock PLL. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-6-angelogioacchino.delregno@somainline.org [sboyd@kernel.org: Grow some local variables, drop do_div() usage in favor of plain division, we're not dealing with a u64 here] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driverMartin Botka
Add a driver for the multimedia clock controller found on SDM660 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by: Martin Botka <martin.botka@somainline.org> Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> [angelogioacchino.delregno@somainline.org: Cleaned up SDM630 clock fixups] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-4-angelogioacchino.delregno@somainline.org [sboyd@kernel.org: Silence NULL pointer sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as criticalAngeloGioacchino Del Regno
This clock is critical for any access to the GPU: gating it will crash the system when the GPU has been initialized (so, you cannot gate it unless you deinit the Adreno completely). So, to achieve a working state with GPU on, set the CLK_IS_CRITICAL flag to this clock. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-3-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as criticalAngeloGioacchino Del Regno
Similarly to MSM8998, any access to the MMSS depends on this clock. Gating it will crash the system when RPMCC inits mmssnoc_axi_rpm_clk. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-2-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate settingAngeloGioacchino Del Regno
The GPU PLL0 is not a fixed PLL and the rate can be set on it: this is necessary especially on boards which bootloader is setting a very low rate on this PLL before booting Linux, which would be unsuitable for postdividing to reach the maximum allowed Adreno GPU frequency of 710MHz (or, actually, even 670MHz..) on this SoC. To allow setting rates on the GPU PLL0, also define VCO boundaries and set the CLK_SET_RATE_PARENT flag to the GPU PLL0 postdivider. With this change, the Adreno GPU is now able to scale through all the available frequencies. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-12-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdscAngeloGioacchino Del Regno
The GPU GX GDSC has GPU_GX_BCR reset and gfx3d_clk CXC, as stated on downstream kernels (and as verified upstream, because otherwise random lockups happen). Also, add PWRSTS_RET and NO_RET_PERIPH: also as found downstream, and also as verified here, to avoid GPU related lockups it is necessary to force retain mem, but *not* peripheral when enabling this GDSC (and, of course, the inverse on disablement). With this change, the GPU finally works flawlessly on my four different MSM8998 devices from two different manufacturers. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-11-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: gdsc: Implement NO_RET_PERIPH flagAngeloGioacchino Del Regno
In some rare occasions, we want to only set the RETAIN_MEM bit, but not the RETAIN_PERIPH one: this is seen on at least SDM630/636/660's GPU-GX GDSC, where unsetting and setting back the RETAIN_PERIPH bit will generate chaos and panics during GPU suspend time (mainly, the chaos is unaligned access). For this reason, introduce a new NO_RET_PERIPH flag to the GDSC driver to address this corner case. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-8-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: mstar: MStar/SigmaStar MPLL driverDaniel Palmer
This adds a basic driver for the MPLL block found in MStar/SigmaStar ARMv7 SoCs. Currently this driver is only good for calculating the rates of it's outputs and the actual configuration must be done before the kernel boots. Usually this is done even before u-boot starts. This driver targets the MPLL block found in the MSC313/MSC313E but there is no documentation this chip so the register descriptions for the another MStar chip the MST786 were used as they seem to match. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Link: https://lore.kernel.org/r/20210211052206.2955988-5-daniel@0x0f.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: fixed: add devm helper for clk_hw_register_fixed_factor()Daniel Palmer
Add a devm helper for clk_hw_register_fixed_factor() so that drivers that internally register fixed factor clocks for things like dividers don't need to manually unregister them on remove or if probe fails. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Link: https://lore.kernel.org/r/20210211052206.2955988-4-daniel@0x0f.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-13Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fix from Stephen Boyd: "One small fix for the Allwinner clk driver so that display clks figure out the correct rate to use. This fixes displays running 4k@60Hz and some other resolutions that haven't been exercised and fully understood until now" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: sunxi-ng: mp: fix parent rate change flag check
2021-02-12clk: socfpga: agilex: add clock driver for eASIC N5X platformDinh Nguyen
Add support for Intel's eASIC N5X platform. The clock manager driver for the N5X is very similar to the Agilex platform, we can re-use most of the Agilex clock driver. This patch makes the necessary changes for the driver to differentiate between the Agilex and the N5X platforms. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210212143059.478554-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: BD718x7: Do not depend on parent driver dataMatti Vaittinen
The bd718x7 only needs a regmap from parent device. This can be obtained by call to dev_get_regmap. Do not require parent to populate the driver data for this. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Link: https://lore.kernel.org/r/20210105123028.GA3409663@localhost.localdomain Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: sunxi-ng: mp: fix parent rate change flag checkJernej Skrabec
CLK_SET_RATE_PARENT flag is checked on parent clock instead of current one. Fix that. Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent rate when allowed") Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Andre Heider <a.heider@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20210209175900.7092-2-jernej.skrabec@siol.net Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: aspeed: Fix APLL calculate formula from ast2600-A2Ryan Chen
Starting from A2, the A-PLL calculation has changed. Use the existing formula for A0/A1 and the new formula for A2 onwards. Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Link: https://lore.kernel.org/r/20210119061715.6043-1-ryan_chen@aspeedtech.com Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: si570: Skip NVM to RAM recall operation if an optional property is setSaeed Nowshadi
Recalling NVM data into RAM during probe() initiates a re-calibration of the clock. If the clock is already in-use, the recall operation can cause a glitch on the frequency out. At power on, the factory data are loaded from NVM into RAM by default. If the clock frequency has been changed since power on, the recall operation can be used to re-initialize the clock to factory setting. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com> Link: https://lore.kernel.org/r/1612496104-3437-3-git-send-email-saeed.nowshadi@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: vc5: Add support for optional load capacitanceAdam Ford
There are two registers which can set the load capacitance for XTAL1 and XTAL2. These are optional registers when using an external crystal. Parse the device tree and set the corresponding registers accordingly. Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20210207185140.3653350-2-aford173@gmail.com Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: zynq: clkc: Remove various instances of an unused variable 'clk'Lee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/zynq/clkc.c: In function ‘zynq_clk_register_fclk’: drivers/clk/zynq/clkc.c:106:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] drivers/clk/zynq/clkc.c: In function ‘zynq_clk_register_periph_clk’: drivers/clk/zynq/clkc.c:179:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] drivers/clk/zynq/clkc.c: In function ‘zynq_clk_setup’: drivers/clk/zynq/clkc.c:220:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-21-lee.jones@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: versatile: clk-icst: Fix worthy struct documentation blockLee Jones
Also demote non-worthy header to standard comment block. Fixes the following W=1 kernel build warning(s): drivers/clk/versatile/clk-icst.c:53: warning: Function parameter or member 'map' not described in 'clk_icst' drivers/clk/versatile/clk-icst.c:53: warning: Function parameter or member 'vcoreg_off' not described in 'clk_icst' drivers/clk/versatile/clk-icst.c:53: warning: Function parameter or member 'lockreg_off' not described in 'clk_icst' drivers/clk/versatile/clk-icst.c:435: warning: cannot understand function prototype: 'const struct icst_params icst525_apcp_cm_params = ' Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-20-lee.jones@linaro.org Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: ti: gate: Fix possible doc-rot in ↵Lee Jones
'omap36xx_gate_clk_enable_with_hsdiv_restore' Fixes the following W=1 kernel build warning(s): drivers/clk/ti/gate.c:67: warning: Function parameter or member 'hw' not described in 'omap36xx_gate_clk_enable_with_hsdiv_restore' drivers/clk/ti/gate.c:67: warning: Excess function parameter 'clk' description in 'omap36xx_gate_clk_enable_with_hsdiv_restore' Cc: Tero Kristo <kristo@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-omap@vger.kernel.org Cc: linux-clk@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-17-lee.jones@linaro.org Reviewed-by: Tero Kristo <kristo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: ti: dpll: Fix misnaming of '_register_dpll()'s 'user' parameterLee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/ti/dpll.c:163: warning: Function parameter or member 'user' not described in '_register_dpll' drivers/clk/ti/dpll.c:163: warning: Excess function parameter 'hw' description in '_register_dpll' Cc: Tero Kristo <kristo@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-omap@vger.kernel.org Cc: linux-clk@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-16-lee.jones@linaro.org Reviewed-by: Tero Kristo <kristo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: ti: clockdomain: Fix description for 'omap2_init_clk_clkdm's hw paramLee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/ti/clockdomain.c:107: warning: Function parameter or member 'hw' not described in 'omap2_init_clk_clkdm' drivers/clk/ti/clockdomain.c:107: warning: Excess function parameter 'clk' description in 'omap2_init_clk_clkdm' Cc: Tero Kristo <kristo@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-omap@vger.kernel.org Cc: linux-clk@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-14-lee.jones@linaro.org Reviewed-by: Tero Kristo <kristo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: st: clkgen-fsyn: Fix worthy struct documentation demote partially ↵Lee Jones
filled one Fixes the following W=1 kernel build warning(s): drivers/clk/st/clkgen-fsyn.c:186: warning: Function parameter or member 'data' not described in 'st_clk_quadfs_pll' drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'regs_base' not described in 'st_clk_quadfs_fsynth' drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'lock' not described in 'st_clk_quadfs_fsynth' drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'data' not described in 'st_clk_quadfs_fsynth' drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'chan' not described in 'st_clk_quadfs_fsynth' drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'md' not described in 'st_clk_quadfs_fsynth' drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'pe' not described in 'st_clk_quadfs_fsynth' drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'sdiv' not described in 'st_clk_quadfs_fsynth' Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Kees Cook <keescook@chromium.org> Cc: Stephen Gallimore <stephen.gallimore@st.com> Cc: Pankaj Dev <pankaj.dev@st.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-13-lee.jones@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: st: clkgen-pll: Demote unpopulated kernel-doc headerLee Jones
And remove an incorrect entry. Fixes the following W=1 kernel build warning(s): drivers/clk/st/clkgen-pll.c:142: warning: cannot understand function prototype: 'struct clkgen_pll ' Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Stephen Gallimore <stephen.gallimore@st.com> Cc: Pankaj Dev <pankaj.dev@st.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-12-lee.jones@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: mvebu: ap-cpu-clk: Demote non-conformant kernel-doc headerLee Jones
Not much effort has been put into this one. Demote it for the time being at least. Fixes the following W=1 kernel build warning(s): drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'ratio_state_reg' not described in 'cpu_dfs_regs' drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'divider_mask' not described in 'cpu_dfs_regs' drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'cluster_offset' not described in 'cpu_dfs_regs' drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'force_mask' not described in 'cpu_dfs_regs' drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'divider_offset' not described in 'cpu_dfs_regs' drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'divider_ratio' not described in 'cpu_dfs_regs' drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'ratio_offset' not described in 'cpu_dfs_regs' drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'ratio_state_offset' not described in 'cpu_dfs_regs' drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'ratio_state_cluster_offset' not described in 'cpu_dfs_regs' Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Julia Lawall <Julia.Lawall@inria.fr> Cc: Omri Itach <omrii@marvell.com> Cc: Gregory Clement <gregory.clement@bootlin.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-10-lee.jones@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc'Lee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/socfpga/clk-pll-a10.c: In function ‘__socfpga_pll_init’: drivers/clk/socfpga/clk-pll-a10.c:76:6: warning: variable ‘rc’ set but not used [-Wunused-but-set-variable] Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-9-lee.jones@linaro.org Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: socfpga: clk-pll: Remove unused variable 'rc'Lee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/socfpga/clk-pll.c: In function ‘__socfpga_pll_init’: drivers/clk/socfpga/clk-pll.c:83:6: warning: variable ‘rc’ set but not used [-Wunused-but-set-variable] Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-8-lee.jones@linaro.org Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: sifive: fu540-prci: Declare static const variable 'prci_clk_fu540' ↵Lee Jones
where it's used Fixes the following W=1 kernel build warning(s): drivers/clk/sifive/fu540-prci.h:16:35: warning: ‘prci_clk_fu540’ defined but not used [-Wunused-const-variable=] drivers/clk/sifive/fu540-prci.h:16:35: warning: ‘prci_clk_fu540’ defined but not used [-Wunused-const-variable=] Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Pragnesh Patel <Pragnesh.patel@sifive.com> Cc: Zong Li <zong.li@sifive.com> Cc: linux-clk@vger.kernel.org Cc: linux-riscv@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-7-lee.jones@linaro.org Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: bcm: clk-iproc-pll: Demote kernel-doc abuseLee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/bcm/clk-iproc-pll.c:712: warning: Function parameter or member 'pll' not described in 'iproc_pll_sw_cfg' Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-6-lee.jones@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: zynqmp: divider: Add missing description for 'max_div'Lee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/zynqmp/divider.c:46: warning: Function parameter or member 'max_div' not described in 'zynqmp_clk_divider' Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Rajan Vaja <rajan.vaja@xilinx.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210126124540.3320214-22-lee.jones@linaro.org Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tero Kristo <kristo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: spear: Move prototype to accessible headerLee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/spear/spear1310_clock.c:385:13: warning: no previous prototype for ‘spear1310_clk_init’ [-Wmissing-prototypes] drivers/clk/spear/spear1340_clock.c:442:13: warning: no previous prototype for ‘spear1340_clk_init’ [-Wmissing-prototypes] Cc: Viresh Kumar <vireshk@kernel.org> Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Rajeev Kumar <rajeev-dlh.kumar@st.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210126124540.3320214-20-lee.jones@linaro.org Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>