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2025-05-30Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This has been a semi-quiet cycle. The core framework remains unchanged this time around. In terms of shiny new code though, we have support for the SpacemiT K1 SoC, Sophgo SG2044, and T-HEAD TH1520 VO clk drivers joining the usual silicon players like Qualcomm, Samsung, Allwinner, and Renesas. Surprisingly, the Qualcomm pile was smaller than usual but that is likely because they put one SoC support inside a driver for a different SoC that is very similar. Other than all those new clk drivers there are the usual clk data updates to fix parents, frequency tables, and add missing clks along with some Kconfig changes to make compile testing simpler and even more DT binding conversions to boot. The exciting part is still the new SoC support like SpacemiT and Sophgo support though, which really dominate the diffstat because they introduce a whole new silicon vendor clk driver. New Drivers: - Camera clock controller driver for Qualcomm QCS8300 - DE (display engine) 3.3 clocks on Allwinner H616 - Samsung ExynosAutov920 CPU cluster CL0, CL1 and CL2 clock controllers - Video Output (VO) subsystem clk controller in the T-HEAD TH1520 SoC - Clock driver for Sophgo SG2044 - Clock driver for SpacemiT K1 SoC - Renesas RZ/V2N (R9A09G056) SoC clk driver Updates: - Correct data in various SoC clk drivers - Allow clkaN to be optional in the Qualcomm RPMh clock controller driver if command db doesn't define it - Change Kconfig options to not enable by default during compile testing - Add missing clks in various SoC clk drivers - Remove some duplicate clk DT bindings and convert some more to YAML" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits) clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750 clk: qcom: rpmh: make clkaN optional clk: qcom: Add support for Camera Clock Controller on QCS8300 clk: rockchip: rk3528: add slab.h header include clk: rockchip: rk3576: add missing slab.h include clk: meson: Do not enable by default during compile testing clk: meson-g12a: add missing fclk_div2 to spicc clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz clk: rockchip: rename gate-grf clk file clk: rockchip: rename branch_muxgrf to branch_grf_mux clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support dt-bindings: allwinner: add H616 DE33 clock binding clk: samsung: correct clock summary for hsi1 block dt-bindings: clock: add SM6350 QCOM video clock bindings clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks clk: sunxi-ng: h616: Add LVDS reset for LCD TCON dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset clk: rockchip: rk3036: mark ddrphy as critical clk: rockchip: rk3036: fix implementation of usb480m clock mux ...
2025-05-29Merge branches 'clk-amlogic', 'clk-allwinner', 'clk-rockchip' and 'clk-qcom' ↵Stephen Boyd
into clk-next * clk-amlogic: clk: meson: Do not enable by default during compile testing clk: meson-g12a: add missing fclk_div2 to spicc * clk-allwinner: clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support dt-bindings: allwinner: add H616 DE33 clock binding clk: sunxi-ng: h616: Add LVDS reset for LCD TCON dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset clk: sunxi: Do not enable by default during compile testing clk: sunxi-ng: Do not enable by default during compile testing * clk-rockchip: clk: rockchip: rk3528: add slab.h header include clk: rockchip: rk3576: add missing slab.h include clk: rockchip: rename gate-grf clk file clk: rockchip: rename branch_muxgrf to branch_grf_mux clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks clk: rockchip: rk3036: mark ddrphy as critical clk: rockchip: rk3036: fix implementation of usb480m clock mux dt-bindings: clock: rk3036: add SCLK_USB480M clock-id clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region clk: rockchip: Support MMC clocks in GRF region dt-bindings: clock: Add GRF clock definition for RK3528 clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576 clk: rockchip: introduce GRF gates clk: rockchip: introduce auxiliary GRFs dt-bindings: clock: rk3576: add IOC gated clocks clk: rockchip: rk3568: Add PLL rate for 33.3MHz clk: rockchip: Drop empty init callback for rk3588 PLL type clk: rockchip: rk3588: Add PLL rate for 1500 MHz * clk-qcom: clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750 clk: qcom: rpmh: make clkaN optional clk: qcom: Add support for Camera Clock Controller on QCS8300 clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz dt-bindings: clock: add SM6350 QCOM video clock bindings clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: Fix missing error check for dev_pm_domain_attach()
2025-05-29Merge branches 'clk-socfpga', 'clk-sophgo', 'clk-thead' and 'clk-samsung' ↵Stephen Boyd
into clk-next * clk-socfpga: clk: socfpga: stratix10: Optimize local variables clk: socfpga: clk-pll: Optimize local variables * clk-sophgo: clk: sophgo: Add clock controller support for SG2044 SoC clk: sophgo: Add PLL clock controller support for SG2044 SoC dt-bindings: clock: sophgo: add clock controller for SG2044 dt-bindings: soc: sophgo: Add SG2044 top syscon device clk: sophgo: Add support for newly added precise compatible dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC * clk-thead: clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC dt-bindings: clock: thead: Add TH1520 VO clock controller * clk-samsung: clk: samsung: correct clock summary for hsi1 block clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition clk: samsung: exynosautov920: add cpucl1/2 clock support dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions clk: samsung: exynosautov920: add cpucl0 clock support dt-bindings: clock: exynosautov920: add cpucl0 clock definitions clk: samsung: Use samsung CCF common function
2025-05-29Merge branches 'clk-bindings', 'clk-renesas', 'clk-spacemit' and ↵Stephen Boyd
'clk-cleanup' into clk-next * clk-bindings: dt-bindings: clock: Drop st,stm32h7-rcc.txt dt-bindings: clock: convert bcm2835-aux-clock to yaml dt-bindings: clock: Drop maxim,max77686.txt dt-bindings: clock: convert vf610-clock.txt to yaml format * clk-renesas: (26 commits) clk: renesas: r9a09g047: Add XSPI clock/reset clk: renesas: r9a09g047: Add support for xspi mux and divider dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks clk: renesas: Use str_on_off() helper clk: renesas: r9a09g057: Add clock and reset entries for USB2 dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable() clk: renesas: rzv2h: Support static dividers without RMW clk: renesas: rzv2h: Add macro for defining static dividers clk: renesas: rzv2h: Add support for static mux clocks clk: renesas: r9a09g047: Add clock and reset entries for GE3D clk: renesas: rzv2h: Fix a typo clk: renesas: rzv2h: Add support for RZ/V2N SoC clk: renesas: rzv2h: Sort compatible list based on SoC part number dt-bindings: pinctrl: renesas: Document RZ/V2N SoC dt-bindings: clock: renesas: Document RZ/V2N SoC CPG dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert() ... * clk-spacemit: clk: spacemit: k1: Add TWSI8 bus and function clocks clk: spacemit: Add clock support for SpacemiT K1 SoC dt-bindings: clock: spacemit: Add spacemit,k1-pll dt-bindings: soc: spacemit: Add spacemit,k1-syscon * clk-cleanup: clk: test: Forward-declare struct of_phandle_args in kunit/clk.h clk: davinci: Use of_get_available_child_by_name() clk: bcm: rpi: Add NULL check in raspberrypi_clk_register() clk: bcm: rpi: Drop module alias clk: bcm: kona: Remove unused scaled_div_build
2025-05-17Merge tag 'sunxi-clk-fixes-for-6.15' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Pull Allwinner clk driver fixes from Chen-Yu Tsai: Only two changes: - Fix the order of arguments in clk macro for SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT that was recently introduced in v6.15-rc1 - Add missing post-divider for D1 MMC clocks to correct halved performance * tag 'sunxi-clk-fixes-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: d1: Add missing divider for MMC mod clocks clk: sunxi-ng: fix order of arguments in clock macro
2025-05-17clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocksTaniya Das
Update the force mem core bit for UFS ICE clock and UFS PHY AXI clock to force the core on signal to remain active during halt state of the clk. If force mem core bit of the clock is not set, the memories of the subsystem will not retain the logic across power states. This is required for the MCQ feature of UFS. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20250414-gcc_ufs_mem_core-v1-2-67b5529b9b5d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-17clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750Taniya Das
Update the force mem core bit for UFS AXI clock to force the core on signal to remain active during halt state of the clk. If force mem core bit of the clock is not set, the memories of the subsystem will not retain the logic across power states. This is required for the MCQ feature of the UFS driver. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20250414-gcc_ufs_mem_core-v1-1-67b5529b9b5d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-17clk: qcom: rpmh: make clkaN optionalPengyu Luo
On SM8650, clkaN are missing in cmd-db for some specific devices. This caused a boot failure. Printing log during initramfs phase, I found [ 0.053281] clk-rpmh 17a00000.rsc:clock-controller: missing RPMh resource address for clka1 Adding the optional property to avoid probing failure which causes countless deferred probe. In the downstream tree,similar workarounds are introduced for SM7635, SM8550, SM8635, SM8650, SM8750. Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Link: https://lore.kernel.org/r/20250413172205.175789-1-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-17clk: qcom: Add support for Camera Clock Controller on QCS8300Imran Shaik
The QCS8300 Camera clock controller is a derivative of SA8775P, but has few additional clocks and offset differences. Hence, add support for QCS8300 Camera clock controller by extending the SA8775P CamCC. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20250327-qcs8300-mm-patches-v6-1-b3fbde2820a6@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-15clk: rockchip: rk3528: add slab.h header includeHeiko Stuebner
The newly added GRF types introduced kzalloc usage into the rk3528. At least for the similar rk3576 driver, the kernel-test-robot reported the missing prototype, which warranted adding a slab.h include. While it did not complain about the rk3528, so the header might be included "accidentially" right now, add a real include to make sure we keep it included in the future. Fixes: 306d2f5ddaa7 ("clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250515082652.2503063-2-heiko@sntech.de
2025-05-15clk: rockchip: rk3576: add missing slab.h includeHeiko Stuebner
The change for auxiliary GRFs introduced kzalloc usage into the rk3576 clock driver, but missed adding the header for its prototype. Add it now. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202505150941.KWKskr2c-lkp@intel.com/ Fixes: 70a114daf207 ("clk: rockchip: introduce auxiliary GRFs") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250515082652.2503063-1-heiko@sntech.de
2025-05-15clk: meson: Do not enable by default during compile testingKrzysztof Kozlowski
Enabling the compile test should not cause automatic enabling of all drivers. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20250404-kconfig-defaults-clk-v1-1-4d2df5603332@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-05-15clk: meson-g12a: add missing fclk_div2 to spiccDa Xue
SPICC is missing fclk_div2, which means fclk_div5 and fclk_div7 indexes are wrong on this clock. This causes the spicc module to output sclk at 2.5x the expected rate when clock index 3 is picked. Adding the missing fclk_div2 resolves this. [jbrunet: amended commit description] Fixes: a18c8e0b7697 ("clk: meson: g12a: add support for the SPICC SCLK Source clocks") Cc: stable@vger.kernel.org # 6.1 Signed-off-by: Da Xue <da@libre.computer> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20250512142617.2175291-1-da@libre.computer Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-05-14clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHzVincent Knecht
Fix mclk0 & mclk1 parent map to use correct GPLL6 configuration and freq_tbl to use GPLL6 instead of GPLL0 so that they tick at 24 MHz. Fixes: 1664014e4679 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller") Suggested-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org> Link: https://lore.kernel.org/r/20250414-gcc-msm8939-fixes-mclk-v2-resend2-v2-1-5ddcf572a6de@mailoo.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-13clk: rockchip: rename gate-grf clk fileHeiko Stuebner
All Rockchip clock types live in files starting with clk-foo, so rename the newly added gate-grf-clock to follow that scheme. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250508182752.1925313-3-heiko@sntech.de
2025-05-13clk: rockchip: rename branch_muxgrf to branch_grf_muxHeiko Stuebner
We now have a number of new branch-types coming from the "General Register Files" (gates and mmc phase clocks). Their naming as branch_grf_foo is way nicer, so rename the old branch_muxgrf to a similar scheme. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250508182752.1925313-2-heiko@sntech.de
2025-05-14clk: sunxi-ng: d1: Add missing divider for MMC mod clocksAndre Przywara
The D1/R528/T113 SoCs have a hidden divider of 2 in the MMC mod clocks, just as other recent SoCs. So far we did not describe that, which led to the resulting MMC clock rate to be only half of its intended value. Use a macro that allows to describe a fixed post-divider, to compensate for that divisor. This brings the MMC performance on those SoCs to its expected level, so about 23 MB/s for SD cards, instead of the 11 MB/s measured so far. Fixes: 35b97bb94111 ("clk: sunxi-ng: Add support for the D1 SoC clocks") Reported-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://patch.msgid.link/20250501120631.837186-1-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-05-12clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) supportRyan Walklin
The DE33 is a newer version of the Allwinner Display Engine IP block, found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already supported by the mainline driver. The DE33 in the H616 has mixer0 and writeback units. The clocks and resets required are identical to the H3 and H5 respectively, so use those existing structs for the H616 description. There are two additional 32-bit registers (at offsets 0x24 and 0x28) which require clearing and setting respectively to bring up the hardware. The function of these registers is currently unknown, and the values are taken from the out-of-tree driver. Add the required clock description struct and compatible string to the DE2 driver. Signed-off-by: Ryan Walklin <ryan@testtoast.com> Link: https://patch.msgid.link/20250511104042.24249-9-ryan@testtoast.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-05-12clk: samsung: correct clock summary for hsi1 blockPritam Manohar Sutar
clk_summary shows wrong value for "mout_hsi1_usbdrd_user". It shows 400Mhz instead of 40Mhz as below. dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ... mout_hsi1_usbdrd_user 0 0 0 400000000 0 0 50000 Y ... dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ... Correct the clk_tree by adding correct clock parent for "mout_hsi1_usbdrd_user". Post this change, clk_summary shows correct value. dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ... mout_clkcmu_hsi1_usbdrd 0 0 0 400000000 0 0 50000 Y ... dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ... mout_hsi1_usbdrd_user 0 0 0 40000000 0 0 50000 Y ... Fixes: 485e13fe2fb6 ("clk: samsung: add top clock support for ExynosAuto v920 SoC") Cc: <stable@kernel.org> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20250506080154.3995512-1-pritam.sutar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-10clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocksYao Zi
This corrects the type and suppresses sparse warnings about passing plain integers as NULL pointer. Fixes: 621ba4d9f6db ("clk: rockchip: Support MMC clocks in GRF region") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202505100302.YVtB1zhF-lkp@intel.com/ Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250510075248.34006-2-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-10clk: sunxi-ng: h616: Add LVDS reset for LCD TCONChris Morgan
Add the required LVDS reset for the LCD TCON. Note that while this reset is exposed for the T507, H616, and H700 only the H700 has an LCD controller. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Ryan Walklin <ryan@testtoast.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Link: https://patch.msgid.link/20250507201943.330111-3-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-05-08clk: s2mps11: initialise clk_hw_onecell_data::num before accessing ::hws[] ↵André Draszik
in probe() With UBSAN enabled, we're getting the following trace: UBSAN: array-index-out-of-bounds in .../drivers/clk/clk-s2mps11.c:186:3 index 0 is out of range for type 'struct clk_hw *[] __counted_by(num)' (aka 'struct clk_hw *[]') This is because commit f316cdff8d67 ("clk: Annotate struct clk_hw_onecell_data with __counted_by") annotated the hws member of that struct with __counted_by, which informs the bounds sanitizer about the number of elements in hws, so that it can warn when hws is accessed out of bounds. As noted in that change, the __counted_by member must be initialised with the number of elements before the first array access happens, otherwise there will be a warning from each access prior to the initialisation because the number of elements is zero. This occurs in s2mps11_clk_probe() due to ::num being assigned after ::hws access. Move the assignment to satisfy the requirement of assign-before-access. Cc: stable@vger.kernel.org Fixes: f316cdff8d67 ("clk: Annotate struct clk_hw_onecell_data with __counted_by") Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20250326-s2mps11-ubsan-v1-1-fcc6fce5c8a9@linaro.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-05-08clk: rockchip: rk3036: mark ddrphy as criticalHeiko Stuebner
The ddrphy is supplied by the dpll, but due to the limited number of PLLs on the rk3036, the dpll also is used for other periperhals, like the GPU. So it happened, when the Lima driver turned off the gpu clock, this in turn also disabled the dpll and thus the ram. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250503202532.992033-4-heiko@sntech.de
2025-05-08clk: rockchip: rk3036: fix implementation of usb480m clock muxHeiko Stuebner
Contrary to how it is implemented right now, this mux is controllable via a bit in CRU_MUSC_CON (same bit as on rk3128 even) and allows switching between xin24m and the 480m output of the usb2phy. So drop the hard-coded fixed-factor clock and implement the correct mux instead. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250503202532.992033-3-heiko@sntech.de
2025-05-08clk: renesas: r9a09g047: Add XSPI clock/resetBiju Das
Add XSPI clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250424081400.135028-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-08clk: renesas: r9a09g047: Add support for xspi mux and dividerBiju Das
The mux smux2_xspi_clk{0,1} used for selecting spi and spix2 clocks and pllcm33_xspi divider to select different clock rates. Add support for both. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250424081400.135028-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-08clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF regionYao Zi
These clocks locate in VO and VPU GRF, serving for SD/SDIO controller tuning purpose. Add their definitions and register them in driver if corresponding GRF is available. GRFs are looked up by compatible to simplify devicetree binding. Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250506092206.46143-4-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-08clk: rockchip: Support MMC clocks in GRF regionYao Zi
Registers of MMC drive/sample clocks in Rockchip RV1106 and RK3528 locate in GRF regions. Adjust MMC clock code to support register operations through regmap. Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250506092206.46143-3-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-07clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoCMichal Wilczynski
The T-Head TH1520 SoC integrates a variety of clocks for its subsystems, including the Application Processor (AP) and the Video Output (VO) [1]. Up until now, the T-Head clock driver only supported AP clocks. Extend the driver to provide clock functionality for the VO subsystem. At this stage, the focus is on implementing the VO clock gates, as these are currently the most relevant and required components for enabling and disabling the VO subsystem functionality. Future enhancements may introduce additional VO-related clocks as necessary. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [1] Reviewed-by: Drew Fustini <drew@pdp7.com> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Signed-off-by: Drew Fustini <drew@pdp7.com>
2025-05-07clk: sophgo: Add clock controller support for SG2044 SoCInochi Amaoto
Add clock driver and clock definition for SG2044 SoC. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/20250418020325.421257-6-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-05-07clk: sophgo: Add PLL clock controller support for SG2044 SoCInochi Amaoto
Add PLL clock driver and clock definition for SG2044 SoC. Link: https://lore.kernel.org/r/20250418020325.421257-5-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-05-07clk: sophgo: Add support for newly added precise compatibleInochi Amaoto
Add of device id definition for newly added precise compatible. Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Link: https://lore.kernel.org/r/20250504104553.1447819-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-05-06clk: davinci: Use of_get_available_child_by_name()Biju Das
Simplify of_davinci_pll_init() by using of_get_available_child_by_name(). While at it, move of_node_put(child) inside the if block to avoid additional check if of_child is NULL. Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20250410062040.6346-1-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-05-06clk: bcm: rpi: Add NULL check in raspberrypi_clk_register()Henry Martin
devm_kasprintf() returns NULL when memory allocation fails. Currently, raspberrypi_clk_register() does not check for this case, which results in a NULL pointer dereference. Add NULL check after devm_kasprintf() to prevent this issue. Fixes: 93d2725affd6 ("clk: bcm: rpi: Discover the firmware clocks") Signed-off-by: Henry Martin <bsdhenrymartin@gmail.com> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20250402020513.42628-1-bsdhenrymartin@gmail.com Reviewed-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-05-06clk: bcm: rpi: Drop module aliasStefan Wahren
Since commit fbac2e7787ac ("clk: bcm: rpi: Allow the driver to be probed by DT") the module alias isn't necessary anymore. So we can drop it. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20250415185614.16292-1-wahrenst@gmx.net Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-05-06clk: bcm: kona: Remove unused scaled_div_buildDr. David Alan Gilbert
scaled_div_build() was added in 2014 by commit 1f27f15258bf ("clk: bcm281xx: add initial clock framework support") but hasn't been used. Remove it. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Link: https://lore.kernel.org/r/20250505013545.359745-1-linux@treblig.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-05-06clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCsLuca Weiss
Compared to the msm-4.19 driver the mainline GDSC driver always sets the bits for en_rest, en_few & clk_dis, and if those values are not set per-GDSC in the respective driver then the default value from the GDSC driver is used. The downstream driver only conditionally sets clk_dis_wait_val if qcom,clk-dis-wait-val is given in devicetree. Correct this situation by explicitly setting those values. For all GDSCs the reset value of those bits are used, with the exception of gpu_cx_gdsc which has an explicit value (qcom,clk-dis-wait-val = <8>). Fixes: 013804a727a0 ("clk: qcom: Add GPU clock controller driver for SM6350") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250425-sm6350-gdsc-val-v1-4-1f252d9c5e4e@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-06clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCsLuca Weiss
Compared to the msm-4.19 driver the mainline GDSC driver always sets the bits for en_rest, en_few & clk_dis, and if those values are not set per-GDSC in the respective driver then the default value from the GDSC driver is used. The downstream driver only conditionally sets clk_dis_wait_val if qcom,clk-dis-wait-val is given in devicetree. Correct this situation by explicitly setting those values. For all GDSCs the reset value of those bits are used. Fixes: 131abae905df ("clk: qcom: Add SM6350 GCC driver") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250425-sm6350-gdsc-val-v1-3-1f252d9c5e4e@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-06clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCsLuca Weiss
Compared to the msm-4.19 driver the mainline GDSC driver always sets the bits for en_rest, en_few & clk_dis, and if those values are not set per-GDSC in the respective driver then the default value from the GDSC driver is used. The downstream driver only conditionally sets clk_dis_wait_val if qcom,clk-dis-wait-val is given in devicetree. Correct this situation by explicitly setting those values. For all GDSCs the reset value of those bits are used. Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250425-sm6350-gdsc-val-v1-2-1f252d9c5e4e@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-06clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCsLuca Weiss
Compared to the msm-4.19 driver the mainline GDSC driver always sets the bits for en_rest, en_few & clk_dis, and if those values are not set per-GDSC in the respective driver then the default value from the GDSC driver is used. The downstream driver only conditionally sets clk_dis_wait_val if qcom,clk-dis-wait-val is given in devicetree. Correct this situation by explicitly setting those values. For all GDSCs the reset value of those bits are used. Fixes: 80f5451d9a7c ("clk: qcom: Add camera clock controller driver for SM6350") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250425-sm6350-gdsc-val-v1-1-1f252d9c5e4e@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-05clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576Nicolas Frattaroli
The Rockchip RK3576 gates the SAI MCLKOUT clocks behind some IOC GRF writes. Add these clock branches, and add the IOC GRF to the auxiliary GRF hashtable. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-4-376cef19dd7c@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-05clk: rockchip: introduce GRF gatesNicolas Frattaroli
Some rockchip SoCs, namely the RK3576, have bits in a General Register File (GRF) that act just like clock gates. The downstream vendor kernel simply maps over the already mapped GRF range with a generic clock gate driver. This solution isn't suitable for upstream, as a memory range will be in use by multiple drivers at the same time, and it leaks implementation details into the device tree. Instead, implement this with a new clock branch type in the Rockchip clock driver: GRF gates. Somewhat akin to MUXGRF, this clock branch depends on the type of GRF, but functions like a gate instead. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-3-376cef19dd7c@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-05clk: rockchip: introduce auxiliary GRFsNicolas Frattaroli
The MUXGRF clock branch type depends on having access to some sort of GRF as a regmap to be registered. So far, we could easily get away with only ever having one GRF stowed away in the context. However, newer Rockchip SoCs, such as the RK3576, have several GRFs which are relevant for clock purposes. It already depends on the pmu0 GRF for MUXGRF reasons, but could get away with not refactoring this because it didn't need the sysgrf at all, so could overwrite the pointer in the clock provider to the pmu0 grf regmap handle. In preparation for needing to finally access more than one GRF per SoC, let's untangle this. Introduce an auxiliary GRF hashmap, and a GRF type enum. The hashmap is keyed by the enum, and clock branches now have a struct member to store the value of that enum, which defaults to the system GRF. The SoC-specific _clk_init function can then insert pointers to GRF regmaps into the hashmap based on the grf type. During clock branch registration, we then pick the right GRF for each branch from the hashmap if something other than the sys GRF is requested. The reason for doing it with this grf type indirection in the clock branches is so that we don't need to define the MUXGRF branches in a separate step, just to have a direct pointer to a regmap available already. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-2-376cef19dd7c@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-05clk: renesas: Use str_on_off() helperGeert Uytterhoeven
Use the str_on_off() helper instead of open-coding the same operation. Note that this does change the case of the flags, which doesn't matter much for debug messages. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/622f8554dcb815c8fc73511a1a118c1724570fa9.1745840497.git.geert+renesas@glider.be
2025-05-01clk: sunxi-ng: fix order of arguments in clock macroAndre Przywara
When introducing the SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT macro, the order of the last two arguments was different between the users and the definition: features became flags and flags became features. This just didn't end up in a disaster yet because most users ended up passing 0 for both arguments, and other clocks (for the new A523 SoC) are not yet used. Swap the order of the arguments in the definition, so that users stay untouched. Fixes: cdbb9d0d09db ("clk: sunxi-ng: mp: provide wrappers for setting feature flags") Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250430095325.477311-1-andre.przywara@arm.com [wens@csie.org: fix typo in commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-04-30clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definitionShin Son
The CLKS_NR_CPUCL0 macro was incorrectly defined based on a wrong clock ID. It mistakenly referenced CLK_DOUT_CLUSTER0_PERIPHCLK, which corresponds to a cluster peripheral clock, not the last clock ID for CPUCL0 as intended. This patch corrects the definition to use CLK_DOUT_CPUCL0_NOCP + 1, properly matching the last clock ID for CPUCL0 as intended. This error was due to confusion with the hardware diagram, and this patch ensures that the number of clocks for CPUCL0 is correctly defined. Signed-off-by: Shin Son <shin.son@samsung.com> Link: https://lore.kernel.org/r/20250428113517.426987-4-shin.son@samsung.com Fixes: 59636ec89c2c ("clk: samsung: exynosautov920: add cpucl0 clock support") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-04-30clk: samsung: exynosautov920: add cpucl1/2 clock supportShin Son
Register compatible and cmu_info data to support clock CPUCL1/2 (CPU Cluster 1 and CPU Cluster 2), these provide clock for CPUCL1/2_SWTICH/CLUSTER. These clocks are required early during boot for the CPUs, so they are declared using CLK_OF_DECLARE instead of being registered through a platform driver. Signed-off-by: Shin Son <shin.son@samsung.com> Link: https://lore.kernel.org/r/20250428113517.426987-3-shin.son@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-04-27clk: samsung: exynosautov920: add cpucl0 clock supportShin Son
Register compatible and cmu_info data to support clock CPUCL0(CPU Cluster 0), this provides clock for CPUCL0_SWTICH/DBG/CLUSTER. These clocks are required early during boot for the CPUs, so they are declared using CLK_OF_DECLARE instead of being registered through a platform driver. Signed-off-by: Shin Son <shin.son@samsung.com> Link: https://lore.kernel.org/r/20250423044153.1288077-3-shin.son@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-04-27clk: sunxi: Do not enable by default during compile testingKrzysztof Kozlowski
Enabling the compile test should not cause automatic enabling of all drivers. Restrict the default to ARCH also for individual drivers, even though their choice is not visible without selecting parent Kconfig symbol, because otherwise selecting parent would select the child during compile testing. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250404-kconfig-defaults-clk-v1-5-4d2df5603332@linaro.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-04-27clk: sunxi-ng: Do not enable by default during compile testingKrzysztof Kozlowski
Enabling the compile test should not cause automatic enabling of all drivers. Restrict the default to ARCH also for individual drivers, even though their choice is not visible without selecting parent Kconfig symbol, because otherwise selecting parent would select the child during compile testing. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250404-kconfig-defaults-clk-v1-4-4d2df5603332@linaro.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>
generated by cgit (git 2.34.1) at 2025-06-14 10:56:56 +0000