summaryrefslogtreecommitdiff
path: root/drivers/clocksource/timer-riscv.c
AgeCommit message (Expand)Author
2024-03-23Merge tag 'timers-core-2024-03-23' of git://git.kernel.org/pub/scm/linux/kern...Linus Torvalds
2024-03-13clocksource/drivers/timer-riscv: Clear timer interrupt on timer initializationLey Foon Tan
2024-01-22clocksource: extend the max_delta_ns of timer-riscv and timer-clint to ULONG_MAXVincent Chen
2023-12-27clocksource/timer-riscv: Add riscv_clock_shutdown callbackJoshua Yeong
2023-11-10Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds
2023-11-09riscv: Rearrange hwcap.h and cpufeature.hXiao Wang
2023-11-08Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds
2023-10-31clocksource: timer-riscv: Increase rating of clock_event_device for SstcAnup Patel
2023-10-31clocksource: timer-riscv: Don't enable/disable timer interruptAnup Patel
2023-10-11clocksource/timer-riscv: ACPI: Add timer_cannot_wakeup_cpuSunil V L
2023-06-01clocksource/timer-riscv: Add ACPI supportSunil V L
2023-06-01clocksource/timer-riscv: Refactor riscv_timer_init_dt()Sunil V L
2023-02-13clocksource/drivers/riscv: Patch riscv_clock_next_event() jump before first useMatt Evans
2023-02-13clocksource/drivers/riscv: Get rid of clocksource_arch_init() callbackLad Prabhakar
2023-02-13clocksource/drivers/riscv: Increase the clock source ratingSamuel Holland
2023-02-13clocksource/drivers/timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DTAnup Patel
2022-12-01Revert "clocksource/drivers/riscv: Events are stopped during CPU suspend"Conor Dooley
2022-08-11RISC-V: Add Sstc extension supportPalmer Dabbelt
2022-08-11RISC-V: Prefer sstc extension if availableAtish Patra
2022-07-19riscv: cpu: Add 64bit hartid support on RV64Sunil V L
2022-05-18clocksource/drivers/riscv: Events are stopped during CPU suspendSamuel Holland
2021-10-04RISC-V: KVM: Add timer functionalityAtish Patra
2020-08-20RISC-V: Remove CLINT related code from timer and archAnup Patel
2020-06-09clocksource/drivers/timer-riscv: Use per-CPU timer interruptAnup Patel
2020-01-04clocksource: riscv: add notrace to riscv_sched_clockZong Li
2019-11-13riscv: add support for MMIO access to the timer registersChristoph Hellwig
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig
2019-09-05riscv: don't use the rdtime(h) pseudo-instructionsChristoph Hellwig
2019-08-06RISC-V: Remove per cpu clocksourceAtish Patra
2019-03-23clocksource/drivers/riscv: Fix clocksource maskAtish Patra
2019-02-23clocksource/drivers/riscv: Add required checks during clock source initAtish Patra
2018-12-18clocksource/drivers/riscv: Change name riscv_timer to timer-riscvDaniel Lezcano