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path: root/drivers/cxl/acpi.c
AgeCommit message (Expand)Author
2023-07-18cxl/acpi: Return 'rc' instead of '0' in cxl_parse_cfmws()Breno Leitao
2023-07-18cxl/acpi: Fix a use-after-free in cxl_parse_cfmws()Breno Leitao
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams
2023-06-25cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams
2023-06-25cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's portRobert Richter
2023-06-25cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()Robert Richter
2023-06-25cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter
2023-02-10Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams
2023-02-10cxl/dax: Create dax devices for CXL RAM regionsDan Williams
2023-02-07Merge branch 'for-6.3/cxl' into cxl/nextDan Williams
2023-01-26cxl: fix spelling mistakesRandy Dunlap
2023-01-25cxl/pmem: Fix nvdimm unregistration when cxl_pmem driver is absentDan Williams
2022-12-05cxl: update names for interleave ways conversion macrosDave Jiang
2022-12-05cxl: update names for interleave granularity conversion macrosDave Jiang
2022-12-05cxl/acpi: Warn about an invalid CHBCR in an existing CHBS entryRobert Richter
2022-12-05cxl/acpi: Fail decoder add if CXIMS for HBIG is missingAlison Schofield
2022-12-05Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams
2022-12-03cxl/acpi: Support CXL XOR Interleave Math (CXIMS)Alison Schofield
2022-12-03cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter
2022-12-02cxl/ACPI: Register CXL host ports by bridge deviceRobert Richter
2022-12-02tools/testing/cxl: Make mock CEDT parsing more robustDan Williams
2022-12-02cxl/acpi: Move rescan to the workqueueDan Williams
2022-12-01cxl/acpi: Simplify cxl_nvdimm_bridge probingDan Williams
2022-11-14cxl/acpi: Improve debug messages in cxl_acpi_probe()Robert Richter
2022-11-14cxl: Unify debug messages when calling devm_cxl_add_dport()Robert Richter
2022-11-14cxl: Unify debug messages when calling devm_cxl_add_port()Robert Richter
2022-08-01cxl/acpi: Minimize granularity for x1 interleavesDan Williams
2022-08-01cxl/acpi: Autoload driver for 'cxl_acpi' test devicesDan Williams
2022-07-21cxl/port: Record parent dport when adding portsDan Williams
2022-07-21cxl/core: Define a 'struct cxl_root_decoder'Dan Williams
2022-07-21cxl/acpi: Track CXL resources in iomem_resourceDan Williams
2022-07-21cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams
2022-07-09cxl: Introduce cxl_to_{ways,granularity}Dan Williams
2022-07-09cxl/core: Drop ->platform_res attribute for root decodersDan Williams
2022-04-28cxl/acpi: Add root device lockdep validationDan Williams
2022-02-08cxl/core/port: Fix / relax decoder target enumerationDan Williams
2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky
2022-02-08cxl/core/port: Add switch port enumerationDan Williams
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams
2022-02-08cxl/pci: Rename pci.h to cxlpci.hDan Williams
2022-02-08cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams
2022-02-08cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams
2022-02-08cxl: Prove CXL lockingDan Williams
2022-02-08cxl/core/port: Make passthrough decoder init implicitBen Widawsky
2022-02-08cxl/core/port: Clarify decoder creationBen Widawsky
2022-02-08cxl/core: Convert decoder range to resourceBen Widawsky
2022-02-08cxl/acpi: Map component registers for Root PortsBen Widawsky
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