| Age | Commit message (Expand) | Author |
|---|
| 2023-02-10 | Merge branch 'for-6.3/cxl-ram-region' into cxl/next | Dan Williams |
| 2023-02-10 | cxl/dax: Create dax devices for CXL RAM regions | Dan Williams |
| 2023-02-07 | Merge branch 'for-6.3/cxl' into cxl/next | Dan Williams |
| 2023-01-26 | cxl: fix spelling mistakes | Randy Dunlap |
| 2023-01-25 | cxl/pmem: Fix nvdimm unregistration when cxl_pmem driver is absent | Dan Williams |
| 2022-12-05 | cxl: update names for interleave ways conversion macros | Dave Jiang |
| 2022-12-05 | cxl: update names for interleave granularity conversion macros | Dave Jiang |
| 2022-12-05 | cxl/acpi: Warn about an invalid CHBCR in an existing CHBS entry | Robert Richter |
| 2022-12-05 | cxl/acpi: Fail decoder add if CXIMS for HBIG is missing | Alison Schofield |
| 2022-12-05 | Merge branch 'for-6.2/cxl-xor' into for-6.2/cxl | Dan Williams |
| 2022-12-03 | cxl/acpi: Support CXL XOR Interleave Math (CXIMS) | Alison Schofield |
| 2022-12-03 | cxl/acpi: Extract component registers of restricted hosts from RCRB | Robert Richter |
| 2022-12-02 | cxl/ACPI: Register CXL host ports by bridge device | Robert Richter |
| 2022-12-02 | tools/testing/cxl: Make mock CEDT parsing more robust | Dan Williams |
| 2022-12-02 | cxl/acpi: Move rescan to the workqueue | Dan Williams |
| 2022-12-01 | cxl/acpi: Simplify cxl_nvdimm_bridge probing | Dan Williams |
| 2022-11-14 | cxl/acpi: Improve debug messages in cxl_acpi_probe() | Robert Richter |
| 2022-11-14 | cxl: Unify debug messages when calling devm_cxl_add_dport() | Robert Richter |
| 2022-11-14 | cxl: Unify debug messages when calling devm_cxl_add_port() | Robert Richter |
| 2022-08-01 | cxl/acpi: Minimize granularity for x1 interleaves | Dan Williams |
| 2022-08-01 | cxl/acpi: Autoload driver for 'cxl_acpi' test devices | Dan Williams |
| 2022-07-21 | cxl/port: Record parent dport when adding ports | Dan Williams |
| 2022-07-21 | cxl/core: Define a 'struct cxl_root_decoder' | Dan Williams |
| 2022-07-21 | cxl/acpi: Track CXL resources in iomem_resource | Dan Williams |
| 2022-07-21 | cxl/core: Define a 'struct cxl_switch_decoder' | Dan Williams |
| 2022-07-09 | cxl: Introduce cxl_to_{ways,granularity} | Dan Williams |
| 2022-07-09 | cxl/core: Drop ->platform_res attribute for root decoders | Dan Williams |
| 2022-04-28 | cxl/acpi: Add root device lockdep validation | Dan Williams |
| 2022-02-08 | cxl/core/port: Fix / relax decoder target enumeration | Dan Williams |
| 2022-02-08 | cxl/mem: Add the cxl_mem driver | Ben Widawsky |
| 2022-02-08 | cxl/core/port: Add switch port enumeration | Dan Williams |
| 2022-02-08 | cxl/core/port: Remove @host argument for dport + decoder enumeration | Dan Williams |
| 2022-02-08 | cxl/port: Add a driver for 'struct cxl_port' objects | Ben Widawsky |
| 2022-02-08 | cxl/core/hdm: Add CXL standard decoder enumeration to the core | Dan Williams |
| 2022-02-08 | cxl/core: Generalize dport enumeration in the core | Dan Williams |
| 2022-02-08 | cxl/pci: Rename pci.h to cxlpci.h | Dan Williams |
| 2022-02-08 | cxl/port: Up-level cxl_add_dport() locking requirements to the caller | Dan Williams |
| 2022-02-08 | cxl/port: Introduce cxl_port_to_pci_bus() | Dan Williams |
| 2022-02-08 | cxl: Prove CXL locking | Dan Williams |
| 2022-02-08 | cxl/core/port: Make passthrough decoder init implicit | Ben Widawsky |
| 2022-02-08 | cxl/core/port: Clarify decoder creation | Ben Widawsky |
| 2022-02-08 | cxl/core: Convert decoder range to resource | Ben Widawsky |
| 2022-02-08 | cxl/acpi: Map component registers for Root Ports | Ben Widawsky |
| 2021-11-15 | ACPI: NUMA: Add a node and memblk for each CFMWS not in SRAT | Alison Schofield |
| 2021-11-15 | cxl/test: Mock acpi_table_parse_cedt() | Dan Williams |
| 2021-11-15 | cxl/acpi: Convert CFMWS parsing to ACPI sub-table helpers | Dan Williams |
| 2021-10-08 | cxl/acpi: Do not fail cxl_acpi_probe() based on a missing CHBS | Alison Schofield |
| 2021-09-21 | cxl/core: Split decoder setup into alloc + add | Dan Williams |
| 2021-09-21 | cxl/bus: Populate the target list at decoder create | Dan Williams |
| 2021-09-21 | tools/testing/cxl: Introduce a mocked-up CXL port hierarchy | Dan Williams |
