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path: root/drivers/cxl/core/pci.c
AgeCommit message (Expand)Author
2023-05-18cxl: Wait Memory_Info_Valid before access memory related infoDave Jiang
2023-05-18cxl/port: Enable the HDM decoder capability for switch portsDan Williams
2023-05-13cxl: Add missing return to cdat read error pathDave Jiang
2023-04-22cxl/port: Fix port to pci device assumptions in read_cdat_data()Dan Williams
2023-04-18cxl/pci: Rightsize CDAT response allocationLukas Wunner
2023-04-18cxl/pci: Simplify CDAT retrieval error pathDave Jiang
2023-04-18cxl/pci: Use CDAT DOE mailbox created by PCI coreLukas Wunner
2023-04-18cxl/pci: Use synchronous API for DOELukas Wunner
2023-04-03cxl/pci: Handle excessive CDAT lengthLukas Wunner
2023-04-03cxl/pci: Handle truncated CDAT entriesLukas Wunner
2023-04-03cxl/pci: Handle truncated CDAT headerLukas Wunner
2023-03-21cxl/pci: Fix CDAT retrieval on big endianLukas Wunner
2023-02-16Merge branch 'for-6.3/cxl-events' into cxl/nextDan Williams
2023-02-16cxl/trace: Standardize device information outputIra Weiny
2023-02-14Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams
2023-02-14cxl/pci: Remove locked check for dvsec_range_allowed()Dave Jiang
2023-02-14cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang
2023-02-14cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang
2023-02-14cxl/pci: Refactor cxl_hdm_decode_init()Dave Jiang
2023-02-14cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang
2023-02-14cxl/pci: Break out range register decoding from cxl_hdm_decode_init()Dave Jiang
2023-02-10Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams
2023-02-10kernel/range: Uplevel the cxl subsystem's range_contains() helperDan Williams
2023-02-07Merge branch 'for-6.3/cxl' into cxl/nextDan Williams
2023-01-04cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams
2022-12-05Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams
2022-12-03cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams
2022-11-14cxl: Unify debug messages when calling devm_cxl_add_dport()Robert Richter
2022-07-19cxl/port: Read CDAT tableIra Weiny
2022-07-09cxl/core: Drop ->platform_res attribute for root decodersDan Williams
2022-05-20cxl/port: Enable HDM Capability after validating DVSEC RangesDan Williams
2022-05-19cxl/port: Reuse 'struct cxl_hdm' context for hdm initDan Williams
2022-05-19cxl/pci: Drop @info argument to cxl_hdm_decode_init()Dan Williams
2022-05-19cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()Dan Williams
2022-05-19cxl/mem: Skip range enumeration if mem_enable clearDan Williams
2022-05-19cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams
2022-05-19cxl/pci: Move cxl_await_media_ready() to the coreDan Williams
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams
generated by cgit (git 2.34.1) at 2025-03-28 17:54:22 +0000