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path: root/drivers/cxl/cxl.h
AgeCommit message (Expand)Author
2023-04-04cxl/port: Fix find_cxl_root() for RCDs and simplify itDan Williams
2023-04-04cxl/hdm: Skip emulation when driver manages mem_enableDan Williams
2023-02-25Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds
2023-02-14Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams
2023-02-14cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang
2023-02-14cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang
2023-02-14cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang
2023-02-14Merge branch 'for-6.3/cxl' into cxl/nextDan Williams
2023-02-14cxl: add RAS status unmasking for CXLDave Jiang
2023-02-10Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams
2023-02-10cxl/dax: Create dax devices for CXL RAM regionsDan Williams
2023-02-10tools/testing/cxl: Define a fixed volatile configuration to parseDan Williams
2023-02-10cxl/region: Add region autodiscoveryDan Williams
2023-02-10cxl/region: Add a mode attribute for regionsDan Williams
2023-01-27driver core: make struct bus_type.uevent() take a const *Greg Kroah-Hartman
2023-01-26cxl/mem: Wire up event interruptsDavidlohr Bueso
2023-01-26cxl/mem: Read, trace, and clear events on driver loadIra Weiny
2023-01-04cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams
2022-12-05cxl: update names for interleave ways conversion macrosDave Jiang
2022-12-05cxl: update names for interleave granularity conversion macrosDave Jiang
2022-12-05Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams
2022-12-05Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams
2022-12-05Merge branch 'for-6.2/cxl-security' into for-6.2/cxlDan Williams
2022-12-05cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_memDan Williams
2022-12-03cxl/acpi: Support CXL XOR Interleave Math (CXIMS)Alison Schofield
2022-12-03cxl/pci: Add (hopeful) error handling supportDan Williams
2022-12-03cxl/pci: Find and map the RAS Capability StructureDan Williams
2022-12-03cxl/pci: Prepare for mapping RAS Capability StructureDan Williams
2022-12-03cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams
2022-12-03cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter
2022-12-03cxl/region: Manage CPU caches relative to DPA invalidation eventsDan Williams
2022-12-02cxl: add dimm_id support for __nvdimm_create()Dave Jiang
2022-12-02cxl/acpi: Move rescan to the workqueueDan Williams
2022-12-02cxl/pmem: Remove the cxl_pmem_wq and related infrastructureDan Williams
2022-12-02cxl/pmem: Refactor nvdimm device registration, delete the workqueueDan Williams
2022-12-02cxl/region: Drop redundant pmem region release handlingDan Williams
2022-11-14cxl: Replace HDM decoder granularity magic numbersAdam Manzanares
2022-11-14cxl/core: Remove duplicate declaration of devm_cxl_iomap_block()Robert Richter
2022-11-04cxl/region: Fix 'distance' calculation with passthrough portsDan Williams
2022-11-04cxl/pmem: Fix cxl_pmem_region and cxl_memdev leakDan Williams
2022-08-05cxl/region: describe targets and nr_targets members of cxl_region_paramsBagas Sanjaya
2022-08-01cxl/acpi: Minimize granularity for x1 interleavesDan Williams
2022-08-01cxl/region: prevent underflow in ways_to_cxl()Dan Carpenter
2022-07-26cxl/region: Introduce cxl_pmem_region objectsDan Williams
2022-07-26cxl/pmem: Fix offline_nvdimm_bus() to offline by bridgeDan Williams
2022-07-26cxl/region: Add region driver boiler plateDan Williams
2022-07-25cxl/hdm: Commit decoder state to hardwareDan Williams
2022-07-25cxl/region: Program target listsDan Williams
2022-07-25cxl/region: Attach endpoint decodersDan Williams
2022-07-25cxl/acpi: Add a host-bridge index lookup mechanismDan Williams
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