summaryrefslogtreecommitdiff
path: root/drivers/cxl/cxl.h
AgeCommit message (Expand)Author
2024-04-08cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coordDave Jiang
2024-04-08cxl: Fix incorrect region perf data calculationDave Jiang
2024-03-12cxl/region: Add memory hotplug notifier for cxl regionDave Jiang
2024-03-12cxl/region: Calculate performance data for a regionDave Jiang
2024-03-12cxl: Split out host bridge access coordinatesDave Jiang
2024-03-12cxl: Split out combine_coordinates() for common shared usageDave Jiang
2024-03-12ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access c...Dave Jiang
2024-02-16cxl: Fix sysfs export of qos_class for memdevDave Jiang
2024-01-05Merge branch 'for-6.7/cxl' into for-6.8/cxlDan Williams
2024-01-05cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang
2024-01-05cxl: Introduce put_cxl_root() helperDave Jiang
2024-01-04cxl/port: Fix missing target list lockDan Williams
2023-12-22cxl: Add helper function that calculate performance data for downstream portsDave Jiang
2023-12-22cxl: Store the access coordinates for the generic portsDave Jiang
2023-12-22cxl: Calculate and store PCI link latency for the downstream portsDave Jiang
2023-12-22cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang
2023-12-22cxl: Add callback to parse the SSLBIS subtable from CDATDave Jiang
2023-12-22cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang
2023-10-31Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams
2023-10-27cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang
2023-10-27cxl: Add cxl_decoders_committed() helperDave Jiang
2023-10-27cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devmRobert Richter
2023-10-27cxl/pci: Map RCH downstream AER registers for logging protocol errorsTerry Bowman
2023-10-27cxl/pci: Add RCH downstream port AER register discoveryRobert Richter
2023-10-27cxl/port: Remove Component Register base address from struct cxl_portRobert Richter
2023-10-27cxl/port: Rename @comp_map to @reg_map in struct cxl_register_mapRobert Richter
2023-10-27cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams
2023-06-25Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams
2023-06-25Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxlDan Williams
2023-06-25Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams
2023-06-25Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams
2023-06-25cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEMDan Williams
2023-06-25cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams
2023-06-25cxl/regs: Clarify when a 'struct cxl_register_map' is input vs outputDan Williams
2023-06-25cxl/region: Flag partially torn down regions as unusableDan Williams
2023-06-25cxl/region: Move cache invalidation before region teardown, and before setupDan Williams
2023-06-25cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter
2023-06-25cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter
2023-06-25cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter
2023-06-25cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter
2023-06-25cxl/pci: Refactor component register discovery for reuseTerry Bowman
2023-06-25cxl/core/regs: Add @dev to cxl_register_mapRobert Richter
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams
2023-06-25cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter
2023-06-25cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams
2023-06-25cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter
2023-05-30cxl/pci: Find and register CXL PMU devicesJonathan Cameron
2023-05-30cxl: Add functions to get an instance of / count regblocks of a given typeJonathan Cameron
generated by cgit (git 2.34.1) at 2025-03-20 13:30:00 +0000