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path: root/drivers/cxl/cxl.h
AgeCommit message (Expand)Author
2022-11-04cxl/region: Fix 'distance' calculation with passthrough portsDan Williams
2022-11-04cxl/pmem: Fix cxl_pmem_region and cxl_memdev leakDan Williams
2022-08-05cxl/region: describe targets and nr_targets members of cxl_region_paramsBagas Sanjaya
2022-08-01cxl/acpi: Minimize granularity for x1 interleavesDan Williams
2022-08-01cxl/region: prevent underflow in ways_to_cxl()Dan Carpenter
2022-07-26cxl/region: Introduce cxl_pmem_region objectsDan Williams
2022-07-26cxl/pmem: Fix offline_nvdimm_bus() to offline by bridgeDan Williams
2022-07-26cxl/region: Add region driver boiler plateDan Williams
2022-07-25cxl/hdm: Commit decoder state to hardwareDan Williams
2022-07-25cxl/region: Program target listsDan Williams
2022-07-25cxl/region: Attach endpoint decodersDan Williams
2022-07-25cxl/acpi: Add a host-bridge index lookup mechanismDan Williams
2022-07-25cxl/region: Enable the assignment of endpoint decoders to regionsDan Williams
2022-07-25cxl/region: Allocate HPA capacity to regionsDan Williams
2022-07-25cxl/region: Add interleave geometry attributesBen Widawsky
2022-07-25cxl/region: Add a 'uuid' attributeBen Widawsky
2022-07-21cxl/region: Add region creation supportBen Widawsky
2022-07-21cxl/mem: Enumerate port targets before adding endpointsDan Williams
2022-07-21cxl/port: Move dport tracking to an xarrayDan Williams
2022-07-21cxl/port: Move 'cxl_ep' references to an xarray per portDan Williams
2022-07-21cxl/port: Record parent dport when adding portsDan Williams
2022-07-21cxl/port: Record dport in endpoint referencesDan Williams
2022-07-21cxl/hdm: Track next decoder to allocateDan Williams
2022-07-21cxl/hdm: Add 'mode' attribute to decoder objectsDan Williams
2022-07-21cxl/hdm: Enumerate allocated DPADan Williams
2022-07-21cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams
2022-07-21cxl/core: Define a 'struct cxl_root_decoder'Dan Williams
2022-07-21cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams
2022-07-19cxl/port: Read CDAT tableIra Weiny
2022-07-11cxl/pmem: Delete unused nvdimm attributeDan Williams
2022-07-10cxl/port: Cache CXL host bridge dataDan Williams
2022-07-09cxl: Introduce cxl_to_{ways,granularity}Dan Williams
2022-07-09cxl/core: Drop is_cxl_decoder()Dan Williams
2022-07-09cxl/core: Drop ->platform_res attribute for root decodersDan Williams
2022-07-09cxl/core: Rename ->decoder_range ->hpa_rangeDan Williams
2022-06-21cxl/core: Use is_endpoint_decoderBen Widawsky
2022-04-28cxl: Drop cxl_device_lock()Dan Williams
2022-02-08cxl/core/port: Add endpoint decodersBen Widawsky
2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky
2022-02-08cxl/core/port: Add switch port enumerationDan Williams
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams
2022-02-08cxl/pmem: Introduce a find_cxl_root() helperDan Williams
2022-02-08cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams
2022-02-08cxl/core/port: Use dedicated lock for decoder target listDan Williams
2022-02-08cxl: Prove CXL lockingDan Williams
2022-02-08cxl/core: Track port depthBen Widawsky
2022-02-08cxl/core/port: Clarify decoder creationBen Widawsky
generated by cgit (git 2.34.1) at 2025-04-06 20:16:24 +0000