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path: root/drivers/cxl/cxlpci.h
AgeCommit message (Expand)Author
2024-05-08PCI/CXL: Move CXL Vendor ID to pci_ids.hDave Jiang
2024-03-12cxl/pci: Get rid of pointer arithmetic reading CDAT tableRobert Richter
2023-12-22cxl: Calculate and store PCI link latency for the downstream portsDave Jiang
2023-05-30cxl/pci: Find and register CXL PMU devicesJonathan Cameron
2023-05-18cxl: Wait Memory_Info_Valid before access memory related infoDave Jiang
2023-04-03cxl/pci: Handle truncated CDAT entriesLukas Wunner
2023-02-14Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams
2023-02-14cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang
2023-01-26cxl/mem: Wire up event interruptsDavidlohr Bueso
2023-01-04cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams
2022-12-03cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams
2022-07-19cxl/port: Read CDAT tableIra Weiny
2022-05-19cxl/port: Reuse 'struct cxl_hdm' context for hdm initDan Williams
2022-05-19cxl/pci: Drop @info argument to cxl_hdm_decode_init()Dan Williams
2022-05-19cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()Dan Williams
2022-05-19cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams
2022-02-08cxl/pci: Retrieve CXL DVSEC memory infoBen Widawsky
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams
2022-02-08cxl/pci: Rename pci.h to cxlpci.hDan Williams
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