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path: root/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
AgeCommit message (Expand)Author
2024-04-09drm/amd/display: Fix compiler warnings on high compiler warning levelsAric Cyr
2024-04-09drm/amd/display: handle invalid connector indicesJoshua Aberback
2024-02-07drm/amd/display: Drop some unnecessary guardsRodrigo Siqueira
2023-06-09drm/amd/display: Clean FPGA code in dcQingqing Zhuo
2023-03-07drm/amd/display: Rename DCN config to FPHarry Wentland
2022-08-10drm/amd/display: remove header from source fileMagali Lemes
2022-07-25drm/amd/display: move FPU code on dcn21 clk_mgrMelissa Wen
2022-05-26drm/amd/display: Fic incorrect pipe being used for clk updateBhawanpreet Lakha
2022-04-12drm/amd/display: Power down hardware if timer not triggerPaul Hsieh
2022-01-14drm/amd/display: Revert W/A for hard hangs on DCN20/DCN21Mario Limonciello
2021-12-13drm/amd/display: fix function scopesIsabella Basso
2021-12-13drm/amd: add some extra checks that is_dig_enabled is definedMario Limonciello
2021-09-28drm/amd/display: Replace referral of dal with dcQingqing Zhuo
2021-09-14drm/amd/display: Apply w/a for hard hang on HPDQingqing Zhuo
2021-09-14drm/amd/display: Revert "dc: w/a for hard hang on HPD on native DP"Qingqing Zhuo
2021-08-05drm/amd/display: workaround for hard hang on HPD on native DPQingqing Zhuo
2021-06-08drm/amd/display: Revert "Fix clock table filling logic"Ilya Bakoulin
2021-05-19drm/amd/display: treat memory as a single-channel for asymmetric memory V3Hugo Hu
2021-05-10drm/amd/display: Handle potential dpp_inst mismatch with pipe_idxAnthony Wang
2021-05-10drm/amd/display: Fix clock table filling logicIlya Bakoulin
2021-05-10drm/amdgpu/dc: Revert commit "treat memory as a single-channel"Aric Cyr
2021-04-28drm/amd/display: Revert wait vblank on update dpp clockLewis Huang
2021-04-20drm/amd/display: treat memory as a single-channel for asymmetric memory v2Hugo Hu
2021-04-15drm/amd/display: wait vblank when stream enabled and update dpp clockLewis Huang
2021-04-09drm/amd/display: Populate socclk entries for dcn2.1Roman Li
2020-12-23drm/amd/display: always program DPPDTO unless not safe to lowerJake Wang
2020-12-23drm/amd/display: updated wm table for RenoirJake Wang
2020-12-23drm/amd/display: Update RN/VGH active display count workaroundMichael Strauss
2020-12-15drm/amd/display: updated wm table for RenoirJake Wang
2020-12-08drm/amd/display: Add wm table for RenoirSung Lee
2020-12-01drm/amd/display: Init clock value by current vbios CLKsBrandon Syu
2020-11-16drm/amd/display: Increase sr enter/exit in rn ddr4 watermark tableWyatt Wood
2020-11-16drm/amd/display: set dpp dto as per requested clk for lower case.Yongqiang Sun
2020-11-16drm/amd/display: Program dpp dto based on actual dpp clkYongqiang Sun
2020-11-10drm/amd/display: check actual clock value.Yongqiang Sun
2020-11-10drm/amd/display: update dpp dto phase and modulo.Yongqiang Sun
2020-10-26drm/amd/display: DCN2.1 Disable 48MHz Powerdown Debug OptionSung Lee
2020-09-29drm/amd/display: remove duplicate call to rn_vbios_smu_get_smu_version()Dirk Gouders
2020-09-15drm/amd/display: Check clock table returnRodrigo Siqueira
2020-08-26drm/amd/display: Send DISPLAY_OFF after power down on bootSung Lee
2020-07-14drm/amd/display: reduce sr_xxx_time by 3 us when ppt disableChiawen Huang
2020-07-08drm/amd/display: Request PHYCLK adjustment on PHY enable/disableJoshua Aberback
2020-07-01drm/amd/display: Red screen observed on startupPeikang Zhang
2020-04-07drm/amd/display: Check for null fclk voltage when parsing clock tableMichael Strauss
2020-03-05drm/amd/display: Remove DISPCLK Limit Floor for Certain SMU VersionsSung Lee
2020-02-25drm/amd/display: make some rn_clk_mgr structs and funcs staticAnthony Koo
2020-02-06drm/amd/display: Limit minimum DPPCLK to 100MHz.Yongqiang Sun
2020-02-06drm/amd/display: Add wm ranges to clk_mgrSung Lee
2020-02-06drm/amd/display: Use dcfclk to populate watermark rangesSung Lee
2020-01-16drm/amd/display: Update HDMI hang w/a to apply to all TMDS signalsMichael Strauss
generated by cgit (git 2.34.1) at 2024-05-21 11:34:47 +0000