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path: root/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32
AgeCommit message (Expand)Author
2022-10-10drm/amd/display: Acquire FCLK DPM levels on DCN32Dillon Varone
2022-10-06drm/amd/display: Reorder FCLK P-state switch sequence for DCN32Dillon Varone
2022-09-29drm/amd/display: fill in clock values when DPM is not enabledSamson Tam
2022-07-25drm/amd/display: Drop FPU flags from dcn32_clk_mgrRodrigo Siqueira
2022-07-05drm/amd/display: Switch to correct DTO on HDMIChris Park
2022-07-05drm/amd/display: Add SubVP required codeAlvin Lee
2022-06-30drm/amdgpu/display: add missing FP_START/END checks dcn32_clk_mgr.cAlex Deucher
2022-06-30drm/amd/display: Fix __nedf2 undefined for 32 bit compilationRodrigo Siqueira
2022-06-30drm/amd/display: Fix __muldf3 undefined for 32 bit compilationRodrigo Siqueira
2022-06-23drm/amd/display: Fix indentation in dcn32_get_vco_frequency_from_reg()Nathan Chancellor
2022-06-21drm/amd/display: Drop duplicate defineRodrigo Siqueira
2022-06-21drm/amd/display: Update hook dcn32_funcsRodrigo Siqueira
2022-06-21drm/amd/display: Implement a pme workaround functionChaitanya Dhere
2022-06-21drm/amd/display: Get VCO frequency from registersRodrigo Siqueira
2022-06-21drm/amd/display: Update SW state correctly for FCLKAlvin Lee
2022-06-21drm/amd/display: Fix divide-by-zero in DPPCLK and DISPCLK calculationGeorge Shen
2022-06-21drm/amd/display: Update DPPCLK programming sequenceAlvin Lee
2022-06-21drm/amd/display: Check minimum disp_clk and dpp_clk debug optionRodrigo Siqueira
2022-06-06drm/amdgpu/display: make some functions staticAlex Deucher
2022-06-03drm/amd/display: Implement DTBCLK ref switching on dcn32Alvin Lee
2022-06-03drm/amd/display: Match dprefclk with clk registersSamson Tam
2022-06-03drm/amd/display: cleaning up smu_if to add future flexibilityMartin Leung
2022-06-03drm/amd/display: FCLK P-state support updatesChaitanya Dhere
2022-06-03drm/amd/display: Introduce new update_clocks logicJun Lei
2022-06-03drm/amd/display: Disable DTB Ref Clock Switching in dcn32Dillon Varone
2022-06-03drm/amd/display: Halve DTB Clock Value for DCN32Fangzhi Zuo
2022-06-03drm/amd/display: Add additional guard for FCLK pstate message for DCN321Dillon Varone
2022-06-03drm/amd/display: Implement WM table transfer for DCN32/DCN321Alvin Lee
2022-06-03drm/amd/display: Add guard for FCLK pstate message to PMFW for DCN321Dillon Varone
2022-06-03drm/amd/display: add CLKMGR changes for DCN32/321Aurabindo Pillai
generated by cgit (git 2.34.1) at 2025-04-26 18:21:52 +0000