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path: root/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
AgeCommit message (Expand)Author
2023-06-09drm/amdgpu: setup hw debug registers on driver initializationJonathan Kim
2023-03-13drm/amd/amdgpu: Add missing INT_STAT_DEBUG registers to GC 10.1 and 10.3 headersTom St Denis
2022-09-13drm/amd/amdgpu: update GC 10.3.0 pwrdecTom St Denis
2022-09-07drm/amd/amdgpu: Add missing CGTS*TCC_DISABLE to 10.3 headersTom St Denis
2022-08-16drm/amdgpu: save and restore gc hub regsVictor Zhao
2021-04-09drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headersTom St Denis
2020-10-23drm/amdgpu: add GC 10.3 NOALLOC registersAlex Deucher
2020-09-17drm/amdgpu: add the GC 10.3 VRS registersAlex Deucher
2020-07-27drm/amd/amdgpu: Add RLC_CGTT_MGCG_OVERRIDE to gfx 10.3 headersTom St Denis
2020-07-01drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2)Tom St Denis
2020-07-01drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registersTom St Denis
2020-07-01drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bitsTom St Denis
2020-07-01drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2)Tom St Denis
2020-06-03drm/amdgpu: add GC 10.3 header files (v2)Likun Gao