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path: root/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
AgeCommit message (Expand)Author
2020-02-11drm/amdgpu:/navi10: use the ODCAP enum to index the caps arrayAlex Deucher
2020-02-04drm/amdgpu: update default voltage for boot od table for navi1xAlex Deucher
2020-02-04drm/amdgpu: fetch default VDDC curve voltages (v2)Alex Deucher
2020-02-04drm/amdgpu/smu_v11_0: Correct behavior of restoring default tables (v2)Matt Coffin
2020-02-04drm/amdgpu/navi10: add OD_RANGE for navi overclockingAlex Deucher
2020-02-04drm/amdgpu/navi: fix index for OD MCLKAlex Deucher
2020-02-04drm/amd/powerplay: fix navi10 system intermittent reboot issue V2Evan Quan
2020-01-30drm/amdgpu/navi10: add mclk to navi10_get_clock_by_type_with_latencyAlex Deucher
2020-01-07drm/amd/powerplay: unified VRAM address for driver table interaction with SMU V2Evan Quan
2020-01-07drm/amd/powerplay: cache the watermark settings on system memoryEvan Quan
2020-01-07drm/amdgpu/smu: custom pstate profiling clock frequence for navi series asicsKevin Wang
2020-01-07drm/amdgpu/smu: add helper function smu_get_dpm_level_range() for smu driverKevin Wang
2020-01-07drm/amdgpu/smu: make the set_performance_level logic easier to followAlex Deucher
2019-12-23drm/amdgpu/smu: add peak profile support for navi12Alex Deucher
2019-12-23drm/amdgpu/smu/navi: Adjust default behavior for peak sclk profileAlex Deucher
2019-12-18drm/amdgpu/smu: add metrics table lock for navi (v2)Alex Deucher
2019-12-18drm/amdgpu/smu: fix spellingAlex Deucher
2019-12-03drm/amdgpu/powerplay: unify smu send message functionLikun Gao
2019-11-19drm/amdgpu: split swSMU baco_reset into enter and exitAlex Deucher
2019-11-19drm/amd/powerplay: correct fine grained dpm force level settingEvan Quan
2019-11-19drm/amd/powerplay: issue BTC on Navi during SMU setupEvan Quan
2019-11-19drm/amd/powerplay: add JPEG power control for Navi1xLeo Liu
2019-11-13drm/amd/powerplay: read pcie speed/width info (v2)Kenneth Feng
2019-11-11drm/amdgpu/smu_v11: Unify and fix power limitsMatt Coffin
2019-11-11drm/amdgpu/navi10: Implement od clk printingMatt Coffin
2019-11-11drm/amdgpu/navi10: implement GFXCLK_CURVE overdriveMatt Coffin
2019-11-11drm/amdgpu/navi10: implement sclk/mclk OD via pp_od_clk_voltageMatt Coffin
2019-11-06drm/amd/swSMU: fix smu workload bit map errorKevin Wang
2019-10-25drm/amd/powerplay: clear the swSMU code layerEvan Quan
2019-10-25drm/amd/powerplay: split out those internal used swSMU APIs V2Evan Quan
2019-10-25drm/amd/powerplay: add lock protection for swSMU APIs V2Evan Quan
2019-10-15drm/amd/powerplay: bug fix for pcie parameters overrideKenneth Feng
2019-10-15drm/amd/powerplay: re-enable FW_DSTATE feature bitXiaojie Yuan
2019-10-15drm/amdgpu/swSMU: custom UMD pstate peak clock for navi14Kevin Wang
2019-10-10drm/amdgpu/swSMU/navi: add feature toggles for more thingsAlex Deucher
2019-10-10drm/amd/powerplay: add more feature bitsXiaojie Yuan
2019-10-03drm/amd/powerplay: add sensor lock support for smuKevin Wang
2019-10-03drm/amd/powerplay: change metrics update period from 1ms to 100msKevin Wang
2019-10-03drm/amdgpu/powerplay: add new mapping for APCC_DFLL featureXiaojie Yuan
2019-09-13drm/amd/powerplay: replace smu->table_count with SMU_TABLE_COUNT in smu (v2)Kevin Wang
2019-08-29drm/amd/powerplay: enable jpeg powergating for navi1xXiaojie Yuan
2019-08-27drm/amd/powerplay: Fix an off by one in navi10_get_smu_msg_index()Dan Carpenter
2019-08-23drm/amd/powerpaly: fix navi series custom peak level value errorKevin Wang
2019-08-21drm/amd/powerplay: correct SW smu11 thermal range settingsEvan Quan
2019-08-12drm/amd/powerplay: remove redundant duplicated return checkColin Ian King
2019-08-12drm/amd/powerplay: change smu_read_sensor sequence in smuKenneth Feng
2019-08-12drm/amd/powerplay: re-define smu interface version for smu v11tiancyin
2019-08-06drm/amd/powerplay: Zero initialize some variablesNathan Chancellor
2019-08-02drm/amd/powerplay: correct navi10 vcn powergateEvan Quan
2019-08-02drm/amd/powerplay: honor hw limit on fetching metrics data for navi10Kevin Wang
generated by cgit (git 2.34.1) at 2024-05-22 17:41:08 +0000