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path: root/drivers/gpu/drm/i915/display/intel_color.c
AgeCommit message (Expand)Author
2024-02-09drm/i915/color: Use per-device debugsVille Syrjälä
2023-11-23drm/i915: Fix glk+ degamma LUT conversionsVille Syrjälä
2023-11-23drm/i915: s/clamp()/min()/ in i965_lut_11p6_max_pack()Ville Syrjälä
2023-11-23drm/i915: Adjust LUT rounding rulesVille Syrjälä
2023-10-13drm/i915/dsb: Re-instate DSB for LUT updatesVille Syrjälä
2023-10-10drm/i915: Fix VLV color state readoutVille Syrjälä
2023-09-27drm/i915/dsb: Use DEwake to combat PkgC latencyVille Syrjälä
2023-09-27drm/i915/dsb: Use non-posted register writes for legacy LUTVille Syrjälä
2023-09-27drm/i915/dsb: Load LUTs using the DSB during vblankVille Syrjälä
2023-09-27drm/i915/dsb: Don't use DSB to load the LUTs during full modesetVille Syrjälä
2023-09-07drm/i915: Constify LUT entries in checkerVille Syrjälä
2023-08-25drm/i915/color: move pre-SKL gamma and CSC enable read to intel_colorJani Nikula
2023-08-25drm/i915/color: move SKL+ gamma and CSC enable read to intel_colorJani Nikula
2023-08-25drm/i915: move ILK+ CSC mode read to intel_colorJani Nikula
2023-08-25drm/i915: move HSW+ gamma mode read to intel_colorJani Nikula
2023-08-25drm/i915/color: move CHV CGM pipe mode read to intel_colorJani Nikula
2023-08-25drm/i915/regs: split out intel_color_regs.hJani Nikula
2023-07-27drm/i915/color: Downscale degamma lut values read from hardwareChaitanya Kumar Borah
2023-07-27drm/i915/color: Upscale degamma values for MTLChaitanya Kumar Borah
2023-05-26drm/i915: Implement CTM property support for VLVVille Syrjälä
2023-05-26drm/i915: Always enable CGM CSC on CHVVille Syrjälä
2023-05-26drm/i915: Fix CHV CGM CSC coefficient sign handlingVille Syrjälä
2023-05-26drm/i915: Expose crtc CTM property on ilk/snbVille Syrjälä
2023-05-24drm/i915: Convert INTEL_INFO()->display to a pointerMatt Roper
2023-04-11drm/i915: Implement chv cgm csc readoutVille Syrjälä
2023-04-11drm/i915: Add hardware csc readout for ilk+Ville Syrjälä
2023-04-11drm/i915: Sprinke a few sanity check WARNS during csc assignmentVille Syrjälä
2023-04-11drm/i915: Utilize crtc_state->csc on chvVille Syrjälä
2023-04-11drm/i915: Store ilk+ csc matrices in the crtc stateVille Syrjälä
2023-04-11drm/i915: Start using struct intel_csc_matrix for chv cgm cscVille Syrjälä
2023-04-11drm/i915: Split chv_load_cgm_csc() into piecesVille Syrjälä
2023-04-11drm/i915: Introduce intel_csc_matrix structVille Syrjälä
2023-04-11drm/i915: Fix limited range csc matrixVille Syrjälä
2023-03-21drm/i915: Workaround ICL CSC_MODE sticky armingVille Syrjälä
2023-03-21drm/i915: Add a .color_post_update() hookVille Syrjälä
2023-03-21drm/i915: Move CSC load back into .color_commit_arm() when PSR is enabled on ...Ville Syrjälä
2023-03-21drm/i915: Split icl_color_commit_noarm() from skl_color_commit_noarm()Ville Syrjälä
2023-02-20drm/i915/dsb: Skip DSB command buffer setup if we have no LUTsVille Syrjälä
2023-02-20drm/i915/dsb: Allow vblank synchronized DSB executionVille Syrjälä
2023-02-17drm/i915: s/PIPECONF/TRANSCONF/Ville Syrjälä
2023-02-03drm/i915/dsb: Introduce intel_dsb_finish()Ville Syrjälä
2023-02-03drm/i915/dsb: Split intel_dsb_wait() from intel_dsb_commit()Ville Syrjälä
2023-01-30drm/i915: implement async_flip mode per plane trackingAndrzej Hajda
2023-01-13drm/i915/dsb: Allow the caller to pass in the DSB buffer sizeVille Syrjälä
2023-01-13drm/i915/dsb: Handle the indexed vs. not inside the DSB codeVille Syrjälä
2022-12-13drm/i915: Use ilk_lut_write*() for all ilk+ gamma modesVille Syrjälä
2022-12-13drm/i915: Disable DSB usage specifically for LUTsVille Syrjälä
2022-12-13drm/i915: Make DSB lower levelVille Syrjälä
2022-12-13drm/i915: Move the DSB setup/cleaup into the color codeVille Syrjälä
2022-12-13drm/i915: Move the DSB->mmio fallback into the LUT codeVille Syrjälä
generated by cgit (git 2.34.1) at 2024-06-20 02:36:28 +0000