summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/display/intel_ddi.c
AgeCommit message (Expand)Author
2022-02-21drm/i915/adlp: Add TypeC PHY TBT->DP-alt/legacy mode switch workaroundImre Deak
2022-02-15drm/i915: Change bigjoiner state tracking to use the pipe bitmaskVille Syrjälä
2022-02-15drm/i915: Introduce intel_crtc_is_bigjoiner_{slave,master}()Ville Syrjälä
2022-02-01drm/i915: Move M/N setup to a more logical place on ddi platformsVille Syrjälä
2022-02-01drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n()Ville Syrjälä
2022-02-01drm/i915: Split intel_cpu_transcoder_get_m_n() into M1/N1 vs. M2/N2 variantsVille Syrjälä
2022-02-01drm/i915: Split intel_cpu_transcoder_set_m_n() into M1/N1 vs. M2/N2 variantsVille Syrjälä
2022-02-01drm/i915: Nuke intel_dp_get_m_n()Ville Syrjälä
2022-02-01drm/i915: Nuke intel_dp_set_m_n()Ville Syrjälä
2022-01-28drm/i915: s/gmch_{m,n}/data_{m,n}/Ville Syrjälä
2022-01-26drm/i915: Move dsc/joiner enable into hsw_crtc_enable()Ville Syrjälä
2022-01-24drm/i915: Nuke dg2_ddi_pre_enable_dp()Ville Syrjälä
2022-01-13drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequenceJosé Roberto de Souza
2022-01-11drm/i915: Move TC PHY registers to their own headerMatt Roper
2022-01-11drm/i915: Move combo PHY registers to their own headerMatt Roper
2021-12-09drm/i915: Add privacy-screen support (v3)Hans de Goede
2021-11-10drm/i915: Call intel_update_active_dpll() for both bigjoiner pipesVille Syrjälä
2021-11-03drm/i915: Use intel_de_rmw() for icl combo phy programmingVille Syrjälä
2021-11-03drm/i915: Use intel_de_rmw() for icl mg phy programmingVille Syrjälä
2021-11-03drm/i915: Use intel_de_rmw() for tgl dkl phy programmingVille Syrjälä
2021-11-03drm/i915: Query the vswing levels per-lane for tgl dkl phyVille Syrjälä
2021-11-03drm/i915: Query the vswing levels per-lane for icl mg phyVille Syrjälä
2021-11-03drm/i915: Query the vswing levels per-lane for icl combo phyVille Syrjälä
2021-11-03drm/i915: Stop using group access when progrmming icl combo phy TXVille Syrjälä
2021-11-01drm/i915/hdmi: Turn DP++ TMDS output buffers back on in encoder->shutdown()Ville Syrjälä
2021-10-27drm/i915: Reduce bigjoiner special casingVille Syrjälä
2021-10-27drm/i915: Split PPS write from DSC enableVille Syrjälä
2021-10-27drm/i915: Introduce intel_master_crtc()Ville Syrjälä
2021-10-27Revert "drm/i915/display: Disable audio, DRRS and PSR before planes"Ville Syrjälä
2021-10-19drm/i915: Move intel_ddi_fdi_post_disable() to fdi codeVille Syrjälä
2021-10-19drm/i915: Move iCLKIP readout to the pch codeVille Syrjälä
2021-10-14drm/i915: Add all per-lane register definitions for icl combo phyVille Syrjälä
2021-10-14drm/i915: Extract icl_combo_phy_loadgen_select()Ville Syrjälä
2021-10-14drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuffVille Syrjälä
2021-10-14drm/i915: Use standard form terminating condition for lane for loopsVille Syrjälä
2021-10-14drm/i915: Remove pointless extra namespace from dkl/snps buf trans structsVille Syrjälä
2021-10-12drm/i915/dg2: update link training for 128b/132bJani Nikula
2021-10-05drm/i915/tc: Delete bogus NULL check in intel_ddi_encoder_destroy()Dan Carpenter
2021-10-04drm/i915: Pass the lane to intel_ddi_level()Ville Syrjälä
2021-10-04drm/i915: Nuke intel_ddi_hdmi_num_entries()Ville Syrjälä
2021-10-04drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level()Ville Syrjälä
2021-10-04drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels()Ville Syrjälä
2021-10-04drm/i915: Nuke useless .set_signal_levels() wrappersVille Syrjälä
2021-10-04drm/i915: Generalize .set_signal_levels()Ville Syrjälä
2021-10-04drm/i915: Introduce has_buf_trans_select()Ville Syrjälä
2021-10-04drm/i915: Introduce has_iboost()Ville Syrjälä
2021-09-30drm/i915: s/ddi_translations/trans/Ville Syrjälä
2021-09-30drm/i915: Call intel_ddi_init_dp_buf_reg() earlierVille Syrjälä
2021-09-29drm/i915/tc: Fix TypeC PHY connect/disconnect logic on ADL-PImre Deak
2021-09-29drm/i915/tc: Add/use helpers to retrieve TypeC port propertiesImre Deak
generated by cgit (git 2.34.1) at 2025-04-05 23:28:10 +0000