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path: root/drivers/gpu/drm/i915/display/intel_snps_phy.c
AgeCommit message (Expand)Author
2022-05-25drm/i915/dg2: Support 4k@30 on HDMIVandita Kulkarni
2022-02-24drm/i915/dg2: Skip output init on PHY calibration failureMatt Roper
2022-02-18drm/i915/dg2: Drop 38.4 MHz MPLLB tablesMatt Roper
2022-02-18drm/i915: Fix for PHY_MISC_TC1 offsetJouni Högander
2022-02-17drm/i915/dg2: Print PHY name properly on calibration errorMatt Roper
2022-01-24drm/i915/snps: convert to drm device based loggingJani Nikula
2022-01-11drm/i915: Move SNPS PHY registers to their own headerMatt Roper
2021-12-07drm/i915/snps: use div32 version of MPLLB word clock for UHBRJani Nikula
2021-11-03drm/i915: Query the vswing levels per-lane for snps phyVille Syrjälä
2021-10-14drm/i915: Remove pointless extra namespace from dkl/snps buf trans structsVille Syrjälä
2021-10-04drm/i915: Pass the lane to intel_ddi_level()Ville Syrjälä
2021-10-04drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level()Ville Syrjälä
2021-10-04drm/i915: Nuke useless .set_signal_levels() wrappersVille Syrjälä
2021-09-30drm/i915: s/ddi_translations/trans/Ville Syrjälä
2021-08-30drm/i915/dg2: UHBR tables added for pll programmingAnimesh Manna
2021-08-26drm/i915/snps: constify struct intel_mpllb_state arrays harderJani Nikula
2021-08-13drm/i915/dg2: use existing mechanisms for SNPS PHY translationsJani Nikula
2021-07-29drm/i915/dg2: Update lane disable power state during PSRGwan-gyeong Mun
2021-07-29drm/i915/dg2: Wait for SNPS PHY calibration during display initMatt Roper
2021-07-29drm/i915/dg2: Add vswing programming for SNPS physMatt Roper
2021-07-29drm/i915/dg2: Add MPLLB programming for HDMIMatt Roper
2021-07-29drm/i915/dg2: Add MPLLB programming for SNPS PHYMatt Roper
generated by cgit (git 2.34.1) at 2025-03-20 21:17:25 +0000