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path: root/drivers/gpu/drm/i915/display/intel_snps_phy.h
AgeCommit message (Expand)Author
2025-02-27drm/i915/snps: convert intel_snps_phy.[ch] to struct intel_displayJani Nikula
2025-01-23drm/i915/snps_phy: Use HDMI PLL algorithm for DG2Ankit Nautiyal
2024-03-21drm/i915/snps: pass encoder to intel_snps_phy_update_psr_power_state()Jani Nikula
2023-10-07drm/i915: Simplify snps/c10x DPLL state checker calling convetionVille Syrjälä
2023-10-07drm/i915: Constify the snps/c10x PLL state checkersVille Syrjälä
2022-06-17drm/i915/mpllb: move mpllb state check to intel_snps_phy.cJani Nikula
2021-10-04drm/i915: Nuke useless .set_signal_levels() wrappersVille Syrjälä
2021-08-13drm/i915/dg2: use existing mechanisms for SNPS PHY translationsJani Nikula
2021-07-29drm/i915/dg2: Update lane disable power state during PSRGwan-gyeong Mun
2021-07-29drm/i915/dg2: Wait for SNPS PHY calibration during display initMatt Roper
2021-07-29drm/i915/dg2: Add vswing programming for SNPS physMatt Roper
2021-07-29drm/i915/dg2: Add MPLLB programming for HDMIMatt Roper
2021-07-29drm/i915/dg2: Add MPLLB programming for SNPS PHYMatt Roper
generated by cgit (git 2.34.1) at 2025-08-04 09:10:38 +0000