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path: root/drivers/gpu/drm/i915/display/skl_watermark.c
AgeCommit message (Expand)Author
2024-08-01drm/i915/dpkgc: Add VRR condition for DPKGC EnablementSuraj Kandpal
2024-05-31drm/i915: Plumb the full atomic state into skl_ddb_add_affected_planes()Ville Syrjälä
2024-05-15drm/i915: Handle SKL+ WM/DDB registers next to all other plane registersVille Syrjälä
2024-05-15drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write()Ville Syrjälä
2024-05-15drm/i915: Extract skl_plane_{wm,ddb}_reg_val()Ville Syrjälä
2024-05-15drm/i915: Move skl+ wm/ddb registers to proper headersVille Syrjälä
2024-05-15drm/i915: Extract skl_universal_plane_regs.hVille Syrjälä
2024-05-03drm/i915/xe2hpd: Do not program MBUS_DBOX BW creditsJosé Roberto de Souza
2024-05-03drm/i915: Reject async flips if we need to change DDB/watermarksVille Syrjälä
2024-04-19drm/i915/display: Disable SAGV on bw init, to force QGV point recalculationStanislav Lisovskiy
2024-04-08drm/i915: move i915_fixed.h to display/intel_fixed.hJani Nikula
2024-04-04drm/i915: Optimize out redundant dbuf slice updatesVille Syrjälä
2024-04-04drm/i915: Use a plain old int for the cdclk/mdclk ratioVille Syrjälä
2024-04-04drm/i915: Implement vblank synchronized MBUS join changesStanislav Lisovskiy
2024-04-04drm/i915: Use the correct mdclk/cdclk ratio in MBUS updatesVille Syrjälä
2024-04-04drm/i915: Add debugs for mbus joining and dbuf ratio programmingVille Syrjälä
2024-04-04drm/i915: Extract intel_dbuf_mdclk_min_tracker_update()Ville Syrjälä
2024-04-04drm/i915: Extract intel_dbuf_mbus_join_update()Ville Syrjälä
2024-04-04drm/i915: Relocate intel_mbus_dbox_update()Ville Syrjälä
2024-04-04drm/i915: Loop over all active pipes in intel_mbus_dbox_updateStanislav Lisovskiy
2024-03-13drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changesGustavo Sousa
2024-03-13drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_stateGustavo Sousa
2024-03-13drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update()Gustavo Sousa
2024-02-23drm/i915/lnl: Program PKGC_LATENCY registerSuraj Kandpal
2024-02-02drm/i915: Compute use_sagv_wm differentlyVille Syrjälä
2024-01-22Revert "drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation"Ville Syrjälä
2023-10-26drm/i915/display: Move enable_sagv module parameter under displayJouni Högander
2023-10-07drm/i915: Simplify watermark state checker calling conventionVille Syrjälä
2023-10-07drm/i915: Constify watermark state checkerVille Syrjälä
2023-09-28drm/i915: Rename intel_modeset_all_pipes() to intel_modeset_all_pipes_late()Imre Deak
2023-09-27drm/i915: Introduce skl_watermark_max_latency()Ville Syrjälä
2023-09-21drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocationStanislav Lisovskiy
2023-06-07drm/i915: annotate maybe unused but set intel_crtc_state variablesJani Nikula
2023-05-24drm/i915: Convert INTEL_INFO()->display to a pointerMatt Roper
2023-04-04drm/i915/wm: split out SKL+ watermark regs to a separate fileJani Nikula
2023-03-31drm/i915/psr: Implement Display WA #1136Jouni Högander
2023-03-31drm/i915/psr: Implement Wa_14015648006Jouni Högander
2023-03-25drm/i915: Add i915.enable_sagv modparamVille Syrjälä
2023-03-10drm/i915: Reject wm levels that exceed vblank timeVille Syrjälä
2023-03-10drm/i915: Extract skl_wm_latency()Ville Syrjälä
2023-03-06drm/i915: remove unnecessary intel_pm.h includesJani Nikula
2023-02-16drm/i915: Copy highest enabled wm level to disabled wm levels for gen >= 9Stanislav Lisovskiy
2023-02-15drm/i915/wm: add .get_hw_state to watermark funcsJani Nikula
2023-02-15drm/i915/wm: move remaining watermark code out of intel_pm.cJani Nikula
2023-02-10drm/i915: Replace wm.max_levels with wm.num_levels and use it everywhereVille Syrjälä
2023-02-10drm/i915: Populate wm.max_level for everyoneVille Syrjälä
2023-02-01drm/i915: Expose SAGV state via debugfsVille Syrjälä
2023-02-01drm/i915: Introduce HAS_SAGV()Ville Syrjälä
2023-02-01drm/i915: Don't do the WM0->WM1 copy w/a if WM1 is already enabledVille Syrjälä
2023-01-30drm/i915: implement async_flip mode per plane trackingAndrzej Hajda
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