summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/intel_dsi_pll.c
AgeCommit message (Expand)Author
2015-07-03drm/i915: Changes required to enable DSI Video Mode on CHTGaurav K Singh
2015-07-03drm/i915: Support for higher DSI clkGaurav K Singh
2015-07-03drm/i915/dsi: abstract dsi bpp derivation from pixel formatJani Nikula
2015-05-28drm/i915: s/dpio_lock/sb_lock/Ville Syrjälä
2015-05-20drm/i915/dsi: add support for DSI PLL N1 divisor valuesJani Nikula
2015-05-20drm/i915: clean up dsi pll calculationJani Nikula
2014-12-10drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port CGaurav K Singh
2014-12-05drm/i915: cck reg used for checking DSI Pll lockedGaurav K Singh
2014-12-05drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual linkGaurav K Singh
2014-08-08drm/i915: Align intel_dsi*.c files a bitDaniel Vetter
2014-08-08drm/i915: Add support for Video Burst Mode for MIPI DSIShobhit Kumar
2014-08-07drm/i915: Add correct hw/sw config check for DSI encoderShobhit Kumar
2013-12-11drm/i915: Try harder to get best m, n, p values with minimal errorShobhit Kumar
2013-12-11drm/i915: Compute dsi_clk from pixel clockShobhit Kumar
2013-09-16drm/i915: Use adjusted_mode in DSI PLL calculationsVille Syrjälä
2013-09-04drm/i915: add VLV DSI PLL Calculationsymohanma
generated by cgit (git 2.34.1) at 2025-04-02 01:28:55 +0000