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path: root/drivers/gpu/drm/i915/intel_lrc.c
AgeCommit message (Expand)Author
2015-11-23Merge tag 'v4.4-rc2' into drm-intel-next-queuedDaniel Vetter
2015-11-19Revert "drm/i915: Initialize HWS page address after GPU reset"Arun Siluvery
2015-11-18drm/i915: Type safe register read/writeVille Syrjälä
2015-11-18drm/i915: Wrap context LRI init in a macroVille Syrjälä
2015-11-18drm/i915: Give names to more ring registersVille Syrjälä
2015-11-18drm/i915: Wrap ASSIGN_CTX_{PDP,PM4L} in do {} while(0)Ville Syrjälä
2015-11-18drm/i915: Add wa_ctx_emit_reg()Ville Syrjälä
2015-11-18drm/i915: Add functions to emit register offsets to the ringVille Syrjälä
2015-11-10Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds
2015-10-29drm/i915: make A0 wa's applied to A1Tim Gore
2015-10-28drm/i915: Recover all available ringbuffer space following resetChris Wilson
2015-10-21drm/i915: add helpers for platform specific revision id range checksJani Nikula
2015-10-21drm/i915/bxt: add revision id for A1 stepping and use itJani Nikula
2015-10-20Merge tag 'drm-intel-next-2015-10-10' of git://anongit.freedesktop.org/drm-in...Dave Airlie
2015-10-16Merge commit '06d1ee32a4d25356a710b49d5e95dbdd68bdf505' of git://git.kernel.o...Dave Airlie
2015-10-13drm/i915: Flush pipecontrol post-sync writesChris Wilson
2015-10-07drm/i915: Kill DRI1 cliprectsChris Wilson
2015-09-28drm/i915: Consider HW CSB write pointer before resetting the sw read pointerMichel Thierry
2015-09-23drm/i915: Remove extraneous request cancel.Nick Hoath
2015-09-23drm/i915: Parametrize LRC registersVille Syrjälä
2015-09-22drm/i915: fix handling gen8_emit_flush_coherentl3_wa resultAndrzej Hajda
2015-09-14drm/i915: Fix warnings while make xmldocs caused by intel_lrc.cMasanari Iida
2015-09-14drm/i915: Split alloc from init for lrcNick Hoath
2015-09-14drm/i915/lrc: Prevent preemption when lite-restore is disabledMichel Thierry
2015-09-14drm/i915: WaEnableForceRestoreInCtxtDescForVCS is for video engines onlyMichel Thierry
2015-09-04drm/i915: Refactor common ringbuffer allocation codeChris Wilson
2015-09-02Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter
2015-09-02drm/i915: Always enable execlists on BDW for vgpuZhiyuan Lv
2015-09-02drm/i915: preallocate pdps for 32 bit vgpuZhiyuan Lv
2015-08-26drm/i915/bxt: work around HW coherency issue when accessing GPU seqnoImre Deak
2015-08-26drm/i915: Change SRM, LRM instructions to use correct lengthArun Siluvery
2015-08-24Merge tag 'v4.2-rc8' into drm-nextDave Airlie
2015-08-17drm/i915: Flag the execlists context object as dirty after every useChris Wilson
2015-08-14drm/i915: Integrate GuC-based command submissionAlex Dai
2015-08-14drm/i915: Expose one LRC function for GuC submission modeDave Gordon
2015-08-14drm/i915/gen8: Add 4 level switching infrastructure and lrc supportMichel Thierry
2015-08-14drm/i915: Check idle to active before processing CSQMika Kuoppala
2015-08-14drm/i915: Use masked write for Context Status Buffer PointerMika Kuoppala
2015-07-21drm/i915: Add provision to extend Golden context batchArun Siluvery
2015-07-15Merge tag 'drm-intel-fixes-2015-07-15' into drm-intel-next-queuedDaniel Vetter
2015-07-15drm/i915/gen9: Add WaSetDisablePixMaskCammingAndRhwoInCommonSliceChickenArun Siluvery
2015-07-15drm/i915/gen9: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaroundArun Siluvery
2015-07-15drm/i915/gen9: Add WaDisableCtxRestoreArbitration workaroundArun Siluvery
2015-07-15drm/i915: Enable WA batch buffers for Gen9Arun Siluvery
2015-07-14drm/i915: Added Programming of the MOCSPeter Antoine
2015-07-08drm/i915: Update wa_ctx_emit() macro as per kernel coding guidelinesArun Siluvery
2015-07-06drm/i915: Mark elsps submitted when they are pushed to hwMika Kuoppala
2015-07-06drm/i915: Convert execlists_ctx_descriptor() for requestsMika Kuoppala
2015-07-06drm/i915: Convert execlists_elsp_writ() for requestsMika Kuoppala
2015-07-06drm/i915: Convert intel_lr_context_pin() for requestsMika Kuoppala
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