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path: root/drivers/gpu/drm/i915/intel_runtime_pm.c
AgeCommit message (Expand)Author
2015-10-06drm/i915: Skip CHV PHY asserts until PHY has been fully resetVille Syrjälä
2015-09-30drm/i915: fixup runtime PM handling v2Jesse Barnes
2015-09-30drm/i915/skl: Block disable call for pw1 if dmc firmware is present.Animesh Manna
2015-09-14drm/i915: make CSR firmware messages less verboseJesse Barnes
2015-09-02Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter
2015-09-01drm/i915: Add CHV PHY LDO power sanity checksVille Syrjälä
2015-09-01drm/i915: Add some CHV DPIO lane power state assertsVille Syrjälä
2015-08-31drm/i915/skl: Adding DDI_E power well domainXiong Zhang
2015-08-26drm/i915: Force CL2 off in CHV x1 PHYVille Syrjälä
2015-08-26drm/i915: Enable DPIO SUS clock gating on CHVVille Syrjälä
2015-08-26drm/i915: Trick CL2 into life on CHV when using pipe B with port BVille Syrjälä
2015-08-26drm/i915: Implement PHY lane power gating for CHVVille Syrjälä
2015-08-26drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enableVille Syrjälä
2015-08-26drm/i915: Add locking around chv_phy_control_init()Ville Syrjälä
2015-08-05drm/i915: Extract a intel_power_well_disable() functionDamien Lespiau
2015-08-05drm/i915: Extract a intel_power_well_enable() functionDamien Lespiau
2015-07-13drm/i915: Refactor VLV display power well init/deinitVille Syrjälä
2015-07-13drm/i915: Simplify CHV pipe A power well codeVille Syrjälä
2015-07-13drm/i915: Apply OCD to VLV/CHV DPLL definesVille Syrjälä
2015-07-13drm/i915: Keep GMCH DPLL VGA mode always disabledVille Syrjälä
2015-05-28drm/i915: Throw out WIP CHV power well definitionsVille Syrjälä
2015-05-28drm/i915: Use the default 600ns LDO programming sequence delayVille Syrjälä
2015-05-20drm/i915: Fix typo in intel_runtime_pm.cMasanari Iida
2015-05-08Revert "drm/i915: Hack to tie both common lanes together on chv"Ville Syrjälä
2015-05-08drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHVVille Syrjälä
2015-05-08drm/i915/skl: Make the Misc I/O power well part of the PLLS domainDamien Lespiau
2015-05-08drm/i915/skl: Add the INIT power domain to the MISC I/O power wellDamien Lespiau
2015-05-08drm/i915/skl: Assert the requirements to enter or exit DC6.Suketu Shah
2015-05-08Implement enable/disable for Display C6 stateA.Sunil Kamath
2015-05-08drm/i915/skl: Add DC6 Trigger sequence.Suketu Shah
2015-05-08drm/i915/skl: Assert the requirements to enter or exit DC5.Suketu Shah
2015-05-08drm/i915/skl: Implement enable/disable for Display C5 state.A.Sunil Kamath
2015-05-08drm/i915/skl: Add DC5 Trigger SequenceSuketu Shah
2015-04-16drm/i915/bxt: Implement enable/disable for Display C9 stateA.Sunil Kamath
2015-04-14drm/i915/bxt: Define BXT power domainsSatheeshakrishna M
2015-03-17drm/i915: Spelling s/auxilliary/auxiliary/Geert Uytterhoeven
2015-03-17drm/i915/skl: Restore the DDI translation tables when enabling PW1Damien Lespiau
2015-03-17drm/i915: Remove unused condition in hsw_power_well_post_enable()Damien Lespiau
2015-03-17drm/i915/skl: Restore pipe interrupt registers after power well enablingDamien Lespiau
2015-03-17drm/i915/skl: Mirror what we do on HSW for the power well enable log messageDamien Lespiau
2015-03-17drm/i915/skl: Introduce enable_requested and is_enabled in the power well codeDamien Lespiau
2015-03-17drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe maskDamien Lespiau
2015-02-13drm/i915/skl: Implementation of SKL display power well supportSatheeshakrishna M
2015-01-27drm/i915/skl: Adding power domains for AUX controllersSatheeshakrishna M
2015-01-12Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queuedDaniel Vetter
2015-01-12drm/i915: remove unused power_well/get_cdclk_freq apiImre Deak
2014-12-18drm/i915: Kill check_power_well() callsVille Syrjälä
2014-12-16drm/i915: tame the chattermouth (v2)Rob Clark
2014-12-03drm/i915: Fix short description of intel_display_power_is_enabled()Damien Lespiau
2014-11-17drm/i915: Reinit display irqs and hpd from chv pipe-a power wellVille Syrjälä
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