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path: root/drivers/pci/controller/dwc
AgeCommit message (Expand)Author
2025-05-02PCI: tegra194: Create debugfs directory only when CONFIG_PCIEASPM is enabledHans Zhang
2025-04-28PCI: dwc: Make link training more robust by setting PORT_LOGIC_LINK_WIDTH to ...Wenbin Yao
2025-04-27PCI: dw-rockchip: Fix PHY function call sequence in rockchip_pcie_phy_deinit()Diederik de Haas
2025-04-27PCI: dw-rockchip: Use rockchip_pcie_link_up() to check link up instead of ope...Hans Zhang
2025-04-27PCI: dw-rockchip: Reorganize register and bitfield definitionsHans Zhang
2025-04-27PCI: dw-rockchip: Remove unused PCIE_CLIENT_GENERAL_DEBUG definitionHans Zhang
2025-04-27PCI: imx6: Save and restore the LUT setting during suspend/resume for i.MX95 SoCRichard Zhu
2025-04-27PCI: imx6: Add PLL lock check for i.MX95 SoCRichard Zhu
2025-04-27PCI: imx6: Add workaround for errata ERR051586Richard Zhu
2025-04-27PCI: imx6: Add workaround for errata ERR051624Richard Zhu
2025-04-27PCI: imx6: Toggle the core reset for i.MX95 PCIeRichard Zhu
2025-04-27PCI: imx6: Call dw_pcie_wait_for_link() from start_link() callback only when ...Richard Zhu
2025-04-27PCI: imx6: Skip link up workaround for newer platformsRichard Zhu
2025-04-27PCI: dw-rockchip: Move rockchip_pcie_ep_hide_broken_ats_cap_rk3588() to dw_pc...Shawn Lin
2025-04-27PCI: dw-rockchip: Enable ASPM L0s capability for both RC and EP modesShawn Lin
2025-04-27PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up()Shawn Lin
2025-04-23PCI: qcom: Add support for IPQ5018Nitheesh Sekar
2025-04-23PCI: dwc: Add support for configuring lane equalization presetsKrishna Chaitanya Chundru
2025-04-19PCI: dwc: Update pci->num_lanes to maximum supported link widthKrishna Chaitanya Chundru
2025-04-19PCI: rcar-gen4: set ep BAR4 fixed sizeJerome Brunet
2025-04-07irqdomain: pci: Switch to of_fwnode_handle()Jiri Slaby (SUSE)
2025-03-27Merge branch 'pci/misc'Bjorn Helgaas
2025-03-27Merge branch 'pci/controller/dwc-cpu-addr-fixup'Bjorn Helgaas
2025-03-27Merge branch 'pci/controller/qcom'Bjorn Helgaas
2025-03-27Merge branch 'pci/controller/layerscape'Bjorn Helgaas
2025-03-27Merge branch 'pci/controller/imx6'Bjorn Helgaas
2025-03-27Merge branch 'pci/controller/histb'Bjorn Helgaas
2025-03-27Merge branch 'pci/controller/dwc'Bjorn Helgaas
2025-03-27Merge branch 'pci/controller/amd-mdb'Bjorn Helgaas
2025-03-27Merge branch 'pci/scoped-cleanup'Bjorn Helgaas
2025-03-27Merge branch 'pci/endpoint-test'Bjorn Helgaas
2025-03-27PCI: layerscape: Fix arg_count to syscon_regmap_lookup_by_phandle_args()Ioana Ciornei
2025-03-26PCI: dw-rockchip: Endpoint mode cannot raise INTx interruptsNiklas Cassel
2025-03-24PCI: intel-gw: Remove intel_pcie_cpu_addr()Frank Li
2025-03-24PCI: imx6: Remove imx_pcie_cpu_addr_fixup()Frank Li
2025-03-24PCI: dwc: Use parent_bus_offset to remove need for .cpu_addr_fixup()Frank Li
2025-03-24PCI: dwc: ep: Ensure proper iteration over outbound map windowsFrank Li
2025-03-24PCI: dwc: ep: Use devicetree 'reg[addr_space]' to derive CPU -> ATU addr offsetFrank Li
2025-03-24PCI: dwc: ep: Consolidate devicetree handling in dw_pcie_ep_get_resources()Bjorn Helgaas
2025-03-24PCI: dwc: ep: Call epc_create() early in dw_pcie_ep_init()Bjorn Helgaas
2025-03-24PCI: dwc: Use devicetree 'reg[config]' to derive CPU -> ATU addr offsetFrank Li
2025-03-24PCI: dwc: Add dw_pcie_parent_bus_offset() checking and debugFrank Li
2025-03-24PCI: dwc: Add dw_pcie_parent_bus_offset()Frank Li
2025-03-23PCI: amd-mdb: Add AMD MDB Root Port driverThippeswamy Havalige
2025-03-17PCI: dwc: Consolidate devicetree handling in dw_pcie_host_get_resources()Bjorn Helgaas
2025-03-17PCI: dwc: Call devm_pci_alloc_host_bridge() early in dw_pcie_host_init()Frank Li
2025-03-17PCI: dwc: Rename cpu_addr to parent_bus_addr for ATU configurationFrank Li
2025-03-17PCI: dwc: Use resource start as ioremap() input in dw_pcie_pme_turn_off()Frank Li
2025-03-16PCI: histb: Fix an error handling path in histb_pcie_probe()Christophe JAILLET
2025-03-15PCI: imx6: Use devm_clk_bulk_get_all() to fetch clocksRichard Zhu
generated by cgit (git 2.34.1) at 2025-09-19 04:49:20 +0000