index
:
linux-arm.git
aarch64/hotplug-vcpu/head
aarch64/hotplug-vcpu/v6.5
aarch64/hotplug-vcpu/v6.6
aarch64/hotplug-vcpu/v6.6-rc1
aarch64/hotplug-vcpu/v6.6-rc5
aarch64/hotplug-vcpu/v6.6-rc6
aarch64/hotplug-vcpu/v6.6-rc7
aarch64/hotplug-vcpu/v6.7
aarch64/hotplug-vcpu/v6.7-rc1
aarch64/hotplug-vcpu/v6.7-rc2
aarch64/hotplug-vcpu/v6.7-rc3
aarch64/hotplug-vcpu/v6.7-rc4
aarch64/hotplug-vcpu/v6.7-rc5
aarch64/hotplug-vcpu/v6.8-rc2
aarch64/ktext/head
aarch64/ktext/v6.5
aarch64/ktext/v6.6-rc5
aarch64/ktext/v6.7
adfs
cex7
clearfog
clearfog-4.10
clearfog-4.11
clearfog-4.12
clearfog-4.13
clearfog-4.9
clkdev
csi-v6
devel-stable
drm-armada-devel
drm-armada-devel-4.15
drm-armada-fixes
drm-armada-fixes-4.15
drm-dwhdmi-devel
drm-etnaviv-devel
drm-tda9950-fixes
drm-tda998x-devel
drm-tda998x-fixes
fec-testing
fiq
fixes
fixes-sa1111
for-arm-soc
for-next
hb2
ktext
ktext-current
master
mcbin
mvneta
mvpp2
net-merged
net-next
net-queue
nmi
phy
rtc
sa1100
spectre
to-build
uaccess
vcpu-rmk
wl18xx
zii
Russell King's ARM Linux kernel tree
Russell King
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
tools
/
testing
/
cxl
Age
Commit message (
Expand
)
Author
2022-11-04
tools/testing/cxl: Add a single-port host-bridge regression config
Dan Williams
2022-11-04
tools/testing/cxl: Fix some error exits
Dan Williams
2022-07-25
cxl/hdm: Commit decoder state to hardware
Dan Williams
2022-07-21
cxl/region: Add region creation support
Ben Widawsky
2022-07-21
cxl/core: Define a 'struct cxl_endpoint_decoder'
Dan Williams
2022-07-21
cxl/core: Define a 'struct cxl_switch_decoder'
Dan Williams
2022-07-10
tools/testing/cxl: Fix decoder default state
Dan Williams
2022-07-10
tools/testing/cxl: Add partition support
Dan Williams
2022-07-10
tools/testing/cxl: Expand CFMWS windows
Dan Williams
2022-07-10
tools/testing/cxl: Move cxl_test resources to the top of memory
Dan Williams
2022-07-09
cxl/mem: Convert partition-info to resources
Dan Williams
2022-07-09
cxl/core: Rename ->decoder_range ->hpa_range
Dan Williams
2022-06-28
tools/testing/cxl: Fix cxl_hdm_decode_init() calling convention
Dan Williams
2022-05-19
cxl/port: Reuse 'struct cxl_hdm' context for hdm init
Dan Williams
2022-05-19
cxl/pci: Drop @info argument to cxl_hdm_decode_init()
Dan Williams
2022-05-19
cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()
Dan Williams
2022-05-19
cxl/mem: Consolidate CXL DVSEC Range enumeration in the core
Dan Williams
2022-05-19
cxl/pci: Move cxl_await_media_ready() to the core
Dan Williams
2022-04-12
cxl/mem: Rename cxl_dvsec_decode_init() to cxl_hdm_decode_init()
Dan Williams
2022-02-08
tools/testing/cxl: Add a physical_node link
Dan Williams
2022-02-08
tools/testing/cxl: Enumerate mock decoders
Dan Williams
2022-02-08
tools/testing/cxl: Mock one level of switches
Dan Williams
2022-02-08
tools/testing/cxl: Fix root port to host bridge assignment
Dan Williams
2022-02-08
tools/testing/cxl: Mock dvsec_ranges()
Dan Williams
2022-02-08
cxl/mem: Add the cxl_mem driver
Ben Widawsky
2022-02-08
cxl/memdev: Add numa_node attribute
Dan Williams
2022-02-08
cxl/pci: Emit device serial number
Dan Williams
2022-02-08
cxl/pci: Implement wait for media active
Ben Widawsky
2022-02-08
cxl/core/port: Remove @host argument for dport + decoder enumeration
Dan Williams
2022-02-08
cxl/port: Add a driver for 'struct cxl_port' objects
Ben Widawsky
2022-02-08
cxl/core/hdm: Add CXL standard decoder enumeration to the core
Dan Williams
2022-02-08
cxl/core: Generalize dport enumeration in the core
Dan Williams
2022-02-08
cxl/port: Up-level cxl_add_dport() locking requirements to the caller
Dan Williams
2022-02-08
cxl/pmem: Introduce a find_cxl_root() helper
Dan Williams
2022-02-08
cxl/core/port: Rename bus.c to port.c
Dan Williams
2021-11-15
cxl/test: Mock acpi_table_parse_cedt()
Dan Williams
2021-11-15
tools/testing/cxl: add mock output for the GET_HEALTH_INFO command
Vishal Verma
2021-11-15
cxl/memdev: Change cxl_mem to a more descriptive name
Ira Weiny
2021-09-21
tools/testing/cxl: Introduce a mock memory device + driver
Dan Williams
2021-09-21
tools/testing/cxl: Introduce a mocked-up CXL port hierarchy
Dan Williams