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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/thead,th1520-clk-ap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: T-HEAD TH1520 AP sub-system clock controller
description: |
The T-HEAD TH1520 AP sub-system clock controller configures the
CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures
the clock gates for the HDMI, MIPI and the GPU.
SoC reference manual
https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
maintainers:
- Jisheng Zhang <jszhang@kernel.org>
- Wei Fu <wefu@redhat.com>
- Drew Fustini <dfustini@tenstorrent.com>
properties:
compatible:
enum:
- thead,th1520-clk-ap
- thead,th1520-clk-vo
reg:
maxItems: 1
clocks:
items:
- description: |
One input clock:
- For "thead,th1520-clk-ap": the clock input must be the 24 MHz
main oscillator.
- For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL,
which is configured by the AP clock controller. According to the
TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL
(integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with
a maximum FOUTVCO of 2376 MHz.
"#clock-cells":
const: 1
description:
See <dt-bindings/clock/thead,th1520-clk-ap.h> for valid indices.
required:
- compatible
- reg
- clocks
- "#clock-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/thead,th1520-clk-ap.h>
clock-controller@ef010000 {
compatible = "thead,th1520-clk-ap";
reg = <0xef010000 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
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