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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/xlnx,vcu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LogicoreIP designed compatible with Xilinx ZYNQ family.
maintainers:
- Rohit Visavalia <rohit.visavalia@amd.com>
description:
LogicoreIP design to provide the isolation between processing system
and programmable logic. Also provides the list of register set to configure
the frequency.
properties:
compatible:
items:
- enum:
- xlnx,vcu
- xlnx,vcu-logicoreip-1.0
reg:
maxItems: 1
clocks:
items:
- description: pll ref clocksource
- description: aclk
clock-names:
items:
- const: pll_ref
- const: aclk
reset-gpios:
maxItems: 1
required:
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
fpga {
#address-cells = <2>;
#size-cells = <2>;
xlnx_vcu: vcu@a0040000 {
compatible = "xlnx,vcu-logicoreip-1.0";
reg = <0x0 0xa0040000 0x0 0x1000>;
reset-gpios = <&gpio 78 GPIO_ACTIVE_HIGH>;
clocks = <&si570_1>, <&clkc 71>;
clock-names = "pll_ref", "aclk";
};
};
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