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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/sophgo,sg2044-dwmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo SG2044 DWMAC glue layer
maintainers:
- Inochi Amaoto <inochiama@gmail.com>
select:
properties:
compatible:
contains:
enum:
- sophgo,sg2044-dwmac
required:
- compatible
properties:
compatible:
items:
- const: sophgo,sg2044-dwmac
- const: snps,dwmac-5.30a
reg:
maxItems: 1
clocks:
items:
- description: GMAC main clock
- description: PTP clock
- description: TX clock
clock-names:
items:
- const: stmmaceth
- const: ptp_ref
- const: tx
dma-noncoherent: true
interrupts:
maxItems: 1
interrupt-names:
maxItems: 1
resets:
maxItems: 1
reset-names:
const: stmmaceth
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- interrupt-names
- resets
- reset-names
allOf:
- $ref: snps,dwmac.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
ethernet@30006000 {
compatible = "sophgo,sg2044-dwmac", "snps,dwmac-5.30a";
reg = <0x30006000 0x4000>;
clocks = <&clk 151>, <&clk 152>, <&clk 154>;
clock-names = "stmmaceth", "ptp_ref", "tx";
interrupt-parent = <&intc>;
interrupts = <296 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&rst 30>;
reset-names = "stmmaceth";
snps,multicast-filter-bins = <0>;
snps,perfect-filter-entries = <1>;
snps,aal;
snps,tso;
snps,txpbl = <32>;
snps,rxpbl = <32>;
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
snps,axi-config = <&gmac0_stmmac_axi_setup>;
status = "disabled";
gmac0_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <8>;
snps,rx-sched-wsp;
queue0 {};
queue1 {};
queue2 {};
queue3 {};
queue4 {};
queue5 {};
queue6 {};
queue7 {};
};
gmac0_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <8>;
queue0 {};
queue1 {};
queue2 {};
queue3 {};
queue4 {};
queue5 {};
queue6 {};
queue7 {};
};
gmac0_stmmac_axi_setup: stmmac-axi-config {
snps,blen = <16 8 4 0 0 0 0>;
snps,wr_osr_lmt = <1>;
snps,rd_osr_lmt = <2>;
};
};
|
