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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8064-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. IPQ8064 TLMM block
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Top Level Mode Multiplexer pin controller in Qualcomm IPQ8064 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,ipq8064-pinctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges: true
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-ipq8064-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-ipq8064-tlmm-state"
additionalProperties: false
$defs:
qcom-ipq8064-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-5][0-9]|6[0-8])$"
- enum: [ sdc3_clk, sdc3_cmd, sdc3_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5,
gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@800000 {
compatible = "qcom,ipq8064-pinctrl";
reg = <0x00800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 69>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
uart-state {
rx-pins {
pins = "gpio19";
function = "gsbi5";
bias-pull-up;
};
tx-pins {
pins = "gpio18";
function = "gsbi5";
bias-disable;
};
};
};
|
