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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/mediatek,mt8365-afe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Audio Front End PCM controller for MT8365
maintainers:
- Alexandre Mergnat <amergnat@baylibre.com>
properties:
compatible:
const: mediatek,mt8365-afe-pcm
reg:
maxItems: 1
"#sound-dai-cells":
const: 0
clocks:
items:
- description: 26M clock
- description: mux for audio clock
- description: audio i2s0 mck
- description: audio i2s1 mck
- description: audio i2s2 mck
- description: audio i2s3 mck
- description: engen 1 clock
- description: engen 2 clock
- description: audio 1 clock
- description: audio 2 clock
- description: mux for i2s0
- description: mux for i2s1
- description: mux for i2s2
- description: mux for i2s3
clock-names:
items:
- const: top_clk26m_clk
- const: top_audio_sel
- const: audio_i2s0_m
- const: audio_i2s1_m
- const: audio_i2s2_m
- const: audio_i2s3_m
- const: engen1
- const: engen2
- const: aud1
- const: aud2
- const: i2s0_m_sel
- const: i2s1_m_sel
- const: i2s2_m_sel
- const: i2s3_m_sel
interrupts:
maxItems: 1
power-domains:
maxItems: 1
mediatek,dmic-mode:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Indicates how many data pins are used to transmit two channels of PDM
signal. 1 means two wires, 0 means one wire. Default value is 0.
enum:
- 0 # one wire
- 1 # two wires
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mediatek,mt8365-power.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
audio-controller@11220000 {
compatible = "mediatek,mt8365-afe-pcm";
reg = <0 0x11220000 0 0x1000>;
#sound-dai-cells = <0>;
clocks = <&clk26m>,
<&topckgen CLK_TOP_AUDIO_SEL>,
<&topckgen CLK_TOP_AUD_I2S0_M>,
<&topckgen CLK_TOP_AUD_I2S1_M>,
<&topckgen CLK_TOP_AUD_I2S2_M>,
<&topckgen CLK_TOP_AUD_I2S3_M>,
<&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
<&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
<&topckgen CLK_TOP_AUD_1_SEL>,
<&topckgen CLK_TOP_AUD_2_SEL>,
<&topckgen CLK_TOP_APLL_I2S0_SEL>,
<&topckgen CLK_TOP_APLL_I2S1_SEL>,
<&topckgen CLK_TOP_APLL_I2S2_SEL>,
<&topckgen CLK_TOP_APLL_I2S3_SEL>;
clock-names = "top_clk26m_clk",
"top_audio_sel",
"audio_i2s0_m",
"audio_i2s1_m",
"audio_i2s2_m",
"audio_i2s3_m",
"engen1",
"engen2",
"aud1",
"aud2",
"i2s0_m_sel",
"i2s1_m_sel",
"i2s2_m_sel",
"i2s3_m_sel";
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8365_POWER_DOMAIN_AUDIO>;
mediatek,dmic-mode = <1>;
};
};
...
|
