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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/adi,axi-spi-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AXI SPI Engine Controller
description: |
The AXI SPI Engine controller is part of the SPI Engine framework[1] and
allows memory mapped access to the SPI Engine control bus. This allows it
to be used as a general purpose software driven SPI controller as well as
some optional advanced acceleration and offloading capabilities.
[1] https://wiki.analog.com/resources/fpga/peripherals/spi_engine
maintainers:
- Michael Hennerich <Michael.Hennerich@analog.com>
- Nuno Sá <nuno.sa@analog.com>
allOf:
- $ref: /schemas/spi/spi-controller.yaml#
properties:
compatible:
const: adi,axi-spi-engine-1.00.a
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: The AXI interconnect clock.
- description: The SPI controller clock.
clock-names:
items:
- const: s_axi_aclk
- const: spi_clk
trigger-sources:
description:
An array of trigger source phandles for offload instances. The index in
the array corresponds to the offload instance number.
minItems: 1
maxItems: 32
dmas:
description:
DMA channels connected to the input or output stream interface of an
offload instance.
minItems: 1
maxItems: 32
dma-names:
items:
pattern: "^offload(?:[12]?[0-9]|3[01])-[tr]x$"
minItems: 1
maxItems: 32
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
spi@44a00000 {
compatible = "adi,axi-spi-engine-1.00.a";
reg = <0x44a00000 0x1000>;
interrupts = <0 56 4>;
clocks = <&clkc 15>, <&clkc 15>;
clock-names = "s_axi_aclk", "spi_clk";
trigger-sources = <&trigger_clock>;
dmas = <&dma 0>;
dma-names = "offload0-rx";
#address-cells = <1>;
#size-cells = <0>;
/* SPI devices */
};
|
