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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/actions,owl-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Actions Semi Owl timer
maintainers:
- Andreas Färber <afaerber@suse.de>
description:
Actions Semi Owl SoCs provide 32bit and 2Hz timers.
The 32bit timers support dynamic irq, as well as one-shot mode.
properties:
compatible:
enum:
- actions,s500-timer
- actions,s700-timer
- actions,s900-timer
clocks:
maxItems: 1
interrupts:
minItems: 1
maxItems: 6
interrupt-names:
minItems: 1
maxItems: 6
items:
enum:
- 2hz0
- 2hz1
- timer0
- timer1
- timer2
- timer3
reg:
maxItems: 1
required:
- compatible
- clocks
- interrupts
- interrupt-names
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- actions,s500-timer
then:
properties:
interrupts:
minItems: 4
maxItems: 4
interrupt-names:
items:
- const: 2hz0
- const: 2hz1
- const: timer0
- const: timer1
- if:
properties:
compatible:
contains:
enum:
- actions,s700-timer
- actions,s900-timer
then:
properties:
interrupts:
minItems: 1
maxItems: 1
interrupt-names:
items:
- const: timer1
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
soc {
#address-cells = <1>;
#size-cells = <1>;
timer@b0168000 {
compatible = "actions,s500-timer";
reg = <0xb0168000 0x100>;
clocks = <&hosc>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "2hz0", "2hz1", "timer0", "timer1";
};
};
...
|
