summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/exynos4210.dtsi
blob: e6e62103a71f3f21f7e1583de6a1a30eed68e31b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
/*
 * Samsung's Exynos4210 SoC device tree source
 *
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 * Copyright (c) 2010-2011 Linaro Ltd.
 *		www.linaro.org
 *
 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include "exynos4.dtsi"
#include "exynos4210-pinctrl.dtsi"
#include "exynos4-cpu-thermal.dtsi"

/ {
	compatible = "samsung,exynos4210", "samsung,exynos4";

	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@900 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x900>;
			clocks = <&clock CLK_ARM_CLK>;
			clock-names = "cpu";
			clock-latency = <160000>;

			operating-points = <
				1200000 1250000
				1000000 1150000
				800000	1075000
				500000	975000
				400000	975000
				200000	950000
			>;
			cooling-min-level = <4>;
			cooling-max-level = <2>;
			#cooling-cells = <2>; /* min followed by max */
		};

		cpu@901 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x901>;
		};
	};

	sysram: sysram@02020000 {
		compatible = "mmio-sram";
		reg = <0x02020000 0x20000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x02020000 0x20000>;

		smp-sysram@0 {
			compatible = "samsung,exynos4210-sysram";
			reg = <0x0 0x1000>;
		};

		smp-sysram@1f000 {
			compatible = "samsung,exynos4210-sysram-ns";
			reg = <0x1f000 0x1000>;
		};
	};

	pd_lcd1: lcd1-power-domain@10023CA0 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10023CA0 0x20>;
		#power-domain-cells = <0>;
		label = "LCD1";
	};

	l2c: l2-cache-controller@10502000 {
		compatible = "arm,pl310-cache";
		reg = <0x10502000 0x1000>;
		cache-unified;
		cache-level = <2>;
		arm,tag-latency = <2 2 1>;
		arm,data-latency = <2 2 1>;
	};

	mct: mct@10050000 {
		compatible = "samsung,exynos4210-mct";
		reg = <0x10050000 0x800>;
		interrupt-parent = <&mct_map>;
		interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
		clock-names = "fin_pll", "mct";

		mct_map: mct-map {
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
					<1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
					<2 &combiner 12 6>,
					<3 &combiner 12 7>,
					<4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
					<5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	watchdog: watchdog@10060000 {
		compatible = "samsung,s3c6410-wdt";
		reg = <0x10060000 0x100>;
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_WDT>;
		clock-names = "watchdog";
	};

	clock: clock-controller@10030000 {
		compatible = "samsung,exynos4210-clock";
		reg = <0x10030000 0x20000>;
		#clock-cells = <1>;
	};

	pinctrl_0: pinctrl@11400000 {
		compatible = "samsung,exynos4210-pinctrl";
		reg = <0x11400000 0x1000>;
		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	};

	pinctrl_1: pinctrl@11000000 {
		compatible = "samsung,exynos4210-pinctrl";
		reg = <0x11000000 0x1000>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;

		wakup_eint: wakeup-interrupt-controller {
			compatible = "samsung,exynos4210-wakeup-eint";
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	pinctrl_2: pinctrl@03860000 {
		compatible = "samsung,exynos4210-pinctrl";
		reg = <0x03860000 0x1000>;
	};

	tmu: tmu@100C0000 {
		compatible = "samsung,exynos4210-tmu";
		interrupt-parent = <&combiner>;
		reg = <0x100C0000 0x100>;
		interrupts = <2 4>;
		clocks = <&clock CLK_TMU_APBIF>;
		clock-names = "tmu_apbif";
		samsung,tmu_gain = <15>;
		samsung,tmu_reference_voltage = <7>;
		status = "disabled";
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tmu 0>;

			trips {
			      cpu_alert0: cpu-alert-0 {
				      temperature = <85000>; /* millicelsius */
			      };
			      cpu_alert1: cpu-alert-1 {
				      temperature = <100000>; /* millicelsius */
			      };
			      cpu_alert2: cpu-alert-2 {
				      temperature = <110000>; /* millicelsius */
			      };
			};
		};
	};

	g2d: g2d@12800000 {
		compatible = "samsung,s5pv210-g2d";
		reg = <0x12800000 0x1000>;
		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
		clock-names = "sclk_fimg2d", "fimg2d";
		power-domains = <&pd_lcd0>;
		iommus = <&sysmmu_g2d>;
	};

	camera {
		clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
			 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
		clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";

		fimc_0: fimc@11800000 {
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,cam-if;
		};

		fimc_1: fimc@11810000 {
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,cam-if;
		};

		fimc_2: fimc@11820000 {
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,lcd-wb;
		};

		fimc_3: fimc@11830000 {
			samsung,pix-limits = <1920 8192 1366 1920>;
			samsung,rotators = <0>;
			samsung,mainscaler-ext;
			samsung,lcd-wb;
		};
	};

	mixer: mixer@12C10000 {
		clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
			"sclk_mixer";
		clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
			<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
			<&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
	};

	ppmu_lcd1: ppmu_lcd1@12240000 {
		compatible = "samsung,exynos-ppmu";
		reg = <0x12240000 0x2000>;
		clocks = <&clock CLK_PPMULCD1>;
		clock-names = "ppmu";
		status = "disabled";
	};

	sysmmu_g2d: sysmmu@12A20000 {
		compatible = "samsung,exynos-sysmmu";
		reg = <0x12A20000 0x1000>;
		interrupt-parent = <&combiner>;
		interrupts = <4 7>;
		clock-names = "sysmmu", "master";
		clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
		power-domains = <&pd_lcd0>;
		#iommu-cells = <0>;
	};

	sysmmu_fimd1: sysmmu@12220000 {
		compatible = "samsung,exynos-sysmmu";
		interrupt-parent = <&combiner>;
		reg = <0x12220000 0x1000>;
		interrupts = <5 3>;
		clock-names = "sysmmu", "master";
		clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
		power-domains = <&pd_lcd1>;
		#iommu-cells = <0>;
	};

	bus_dmc: bus_dmc {
		compatible = "samsung,exynos-bus";
		clocks = <&clock CLK_DIV_DMC>;
		clock-names = "bus";
		operating-points-v2 = <&bus_dmc_opp_table>;
		status = "disabled";
	};

	bus_acp: bus_acp {
		compatible = "samsung,exynos-bus";
		clocks = <&clock CLK_DIV_ACP>;
		clock-names = "bus";
		operating-points-v2 = <&bus_acp_opp_table>;
		status = "disabled";
	};

	bus_peri: bus_peri {
		compatible = "samsung,exynos-bus";
		clocks = <&clock CLK_ACLK100>;
		clock-names = "bus";
		operating-points-v2 = <&bus_peri_opp_table>;
		status = "disabled";
	};

	bus_fsys: bus_fsys {
		compatible = "samsung,exynos-bus";
		clocks = <&clock CLK_ACLK133>;
		clock-names = "bus";
		operating-points-v2 = <&bus_fsys_opp_table>;
		status = "disabled";
	};

	bus_display: bus_display {
		compatible = "samsung,exynos-bus";
		clocks = <&clock CLK_ACLK160>;
		clock-names = "bus";
		operating-points-v2 = <&bus_display_opp_table>;
		status = "disabled";
	};

	bus_lcd0: bus_lcd0 {
		compatible = "samsung,exynos-bus";
		clocks = <&clock CLK_ACLK200>;
		clock-names = "bus";
		operating-points-v2 = <&bus_leftbus_opp_table>;
		status = "disabled";
	};

	bus_leftbus: bus_leftbus {
		compatible = "samsung,exynos-bus";
		clocks = <&clock CLK_DIV_GDL>;
		clock-names = "bus";
		operating-points-v2 = <&bus_leftbus_opp_table>;
		status = "disabled";
	};

	bus_rightbus: bus_rightbus {
		compatible = "samsung,exynos-bus";
		clocks = <&clock CLK_DIV_GDR>;
		clock-names = "bus";
		operating-points-v2 = <&bus_leftbus_opp_table>;
		status = "disabled";
	};

	bus_mfc: bus_mfc {
		compatible = "samsung,exynos-bus";
		clocks = <&clock CLK_SCLK_MFC>;
		clock-names = "bus";
		operating-points-v2 = <&bus_leftbus_opp_table>;
		status = "disabled";
	};

	bus_dmc_opp_table: opp_table1 {
		compatible = "operating-points-v2";
		opp-shared;

		opp@134000000 {
			opp-hz = /bits/ 64 <134000000>;
			opp-microvolt = <1025000>;
		};
		opp@267000000 {
			opp-hz = /bits/ 64 <267000000>;
			opp-microvolt = <1050000>;
		};
		opp@400000000 {
			opp-hz = /bits/ 64 <400000000>;
			opp-microvolt = <1150000>;
		};
	};

	bus_acp_opp_table: opp_table2 {
		compatible = "operating-points-v2";
		opp-shared;

		opp@134000000 {
			opp-hz = /bits/ 64 <134000000>;
		};
		opp@160000000 {
			opp-hz = /bits/ 64 <160000000>;
		};
		opp@200000000 {
			opp-hz = /bits/ 64 <200000000>;
		};
	};

	bus_peri_opp_table: opp_table3 {
		compatible = "operating-points-v2";
		opp-shared;

		opp@5000000 {
			opp-hz = /bits/ 64 <5000000>;
		};
		opp@100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};
	};

	bus_fsys_opp_table: opp_table4 {
		compatible = "operating-points-v2";
		opp-shared;

		opp@10000000 {
			opp-hz = /bits/ 64 <10000000>;
		};
		opp@134000000 {
			opp-hz = /bits/ 64 <134000000>;
		};
	};

	bus_display_opp_table: opp_table5 {
		compatible = "operating-points-v2";
		opp-shared;

		opp@100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};
		opp@134000000 {
			opp-hz = /bits/ 64 <134000000>;
		};
		opp@160000000 {
			opp-hz = /bits/ 64 <160000000>;
		};
	};

	bus_leftbus_opp_table: opp_table6 {
		compatible = "operating-points-v2";
		opp-shared;

		opp@100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};
		opp@160000000 {
			opp-hz = /bits/ 64 <160000000>;
		};
		opp@200000000 {
			opp-hz = /bits/ 64 <200000000>;
		};
	};
};

&gic {
	cpu-offset = <0x8000>;
};

&combiner {
	samsung,combiner-nr = <16>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};

&mdma1 {
	power-domains = <&pd_lcd0>;
};

&pmu_system_controller {
	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
			"clkout4", "clkout8", "clkout9";
	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
		<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
		<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
	#clock-cells = <1>;
};

&rotator {
	power-domains = <&pd_lcd0>;
};

&sysmmu_rotator {
	power-domains = <&pd_lcd0>;
};