summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
blob: 5761a66e8a0d3736f9c4776690174883bdb2dd14 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
/*
 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx51.dtsi"

/ {
	model = "Digi ConnectCore CC(W)-MX51";
	compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51";

	memory@90000000 {
		reg = <0x90000000 0x08000000>;
	};
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
	status = "okay";

	pmic: mc13892@0 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mc13892>;
		compatible = "fsl,mc13892";
		spi-max-frequency = <16000000>;
		spi-cs-high;
		reg = <0>;
		interrupt-parent = <&gpio1>;
		interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
		fsl,mc13xxx-uses-rtc;

		regulators {
			sw1_reg: sw1 {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1100000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <1225000>;
				regulator-max-microvolt = <1225000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3_reg: sw3 {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-boot-on;
				regulator-always-on;
			};

			swbst_reg: swbst { };

			viohi_reg: viohi {
				regulator-always-on;
			};

			vpll_reg: vpll {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			vdig_reg: vdig {
				regulator-min-microvolt = <1250000>;
				regulator-max-microvolt = <1250000>;
				regulator-always-on;
			};

			vsd_reg: vsd {
				regulator-min-microvolt = <3150000>;
				regulator-max-microvolt = <3150000>;
				regulator-always-on;
			};

			vusb2_reg: vusb2 {
				regulator-min-microvolt = <2600000>;
				regulator-max-microvolt = <2600000>;
				regulator-always-on;
			};

			vvideo_reg: vvideo {
				regulator-min-microvolt = <2775000>;
				regulator-max-microvolt = <2775000>;
				regulator-always-on;
			};

			vaudio_reg: vaudio {
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
			};

			vcam_reg: vcam {
				regulator-min-microvolt = <2750000>;
				regulator-max-microvolt = <2750000>;
				regulator-always-on;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-always-on;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <3150000>;
				regulator-max-microvolt = <3150000>;
				regulator-always-on;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			vusb_reg: vusb {
				regulator-always-on;
			};

			gpo1_reg: gpo1 { };

			gpo2_reg: gpo2 { };

			gpo3_reg: gpo3 { };

			gpo4_reg: gpo4 { };

			pwgt2spi_reg: pwgt2spi {
				regulator-always-on;
			};

			vcoincell_reg: vcoincell {
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
			};
		};
	};
};

&esdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc2>;
	cap-sdio-irq;
	wakeup-source;
	keep-power-in-suspend;
	max-frequency = <50000000>;
	no-1-8-v;
	non-removable;
	vmmc-supply = <&gpo4_reg>;
	status = "okay";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "mii";
	phy-supply = <&gpo3_reg>;
	/* Pins shared with LCD2, keep status disabled */
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clock-frequency = <400000>;
	status = "okay";

	mma7455l@1d {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mma7455l>;
		compatible = "fsl,mma7455l";
		reg = <0x1d>;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>;
	};
};

&nfc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nfc>;
	nand-bus-width = <8>;
	nand-ecc-mode = "hw";
	nand-on-flash-bbt;
	status = "okay";
};

&usbotg {
	phy_type = "utmi_wide";
	disable-over-current;
	/* Device role is not known, keep status disabled */
};

&weim {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_weim>;
	status = "okay";

	lan9221: lan9221@5,0 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lan9221>;
		compatible = "smsc,lan9221", "smsc,lan9115";
		reg = <5 0x00000000 0x1000>;
		fsl,weim-cs-timing = <
			0x00420081 0x00000000
			0x32260000 0x00000000
			0x72080f00 0x00000000
		>;
		clocks = <&clks IMX5_CLK_DUMMY>;
		interrupt-parent = <&gpio1>;
		interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
		phy-mode = "mii";
		reg-io-width = <2>;
		smsc,irq-push-pull;
		vdd33a-supply = <&gpo2_reg>;
		vddvario-supply = <&gpo2_reg>;
	};
};

&iomuxc {
	imx51-digi-connectcore-som {
		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX51_PAD_CSPI1_MISO__ECSPI1_MISO	0x185
				MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	0x185
				MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	0x185
				MX51_PAD_CSPI1_SS0__GPIO4_24		0x85 /* CS0 */
			>;
		};

		pinctrl_esdhc2: esdhc2grp {
			fsl,pins = <
				MX51_PAD_SD2_CMD__SD2_CMD		0x400020d5
				MX51_PAD_SD2_CLK__SD2_CLK		0x20d5
				MX51_PAD_SD2_DATA0__SD2_DATA0		0x20d5
				MX51_PAD_SD2_DATA1__SD2_DATA1		0x20d5
				MX51_PAD_SD2_DATA2__SD2_DATA2		0x20d5
				MX51_PAD_SD2_DATA3__SD2_DATA3		0x20d5
			>;
		};

		pinctrl_fec: fecgrp {
			fsl,pins = <
				MX51_PAD_DI_GP3__FEC_TX_ER		0x80000000
				MX51_PAD_DI2_PIN4__FEC_CRS		0x80000000
				MX51_PAD_DI2_PIN2__FEC_MDC		0x80000000
				MX51_PAD_DI2_PIN3__FEC_MDIO		0x80000000
				MX51_PAD_DI2_DISP_CLK__FEC_RDATA1	0x80000000
				MX51_PAD_DI_GP4__FEC_RDATA2		0x80000000
				MX51_PAD_DISP2_DAT0__FEC_RDATA3		0x80000000
				MX51_PAD_DISP2_DAT1__FEC_RX_ER		0x80000000
				MX51_PAD_DISP2_DAT6__FEC_TDATA1		0x80000000
				MX51_PAD_DISP2_DAT7__FEC_TDATA2		0x80000000
				MX51_PAD_DISP2_DAT8__FEC_TDATA3		0x80000000
				MX51_PAD_DISP2_DAT9__FEC_TX_EN		0x80000000
				MX51_PAD_DISP2_DAT10__FEC_COL		0x80000000
				MX51_PAD_DISP2_DAT11__FEC_RX_CLK	0x80000000
				MX51_PAD_DISP2_DAT12__FEC_RX_DV		0x80000000
				MX51_PAD_DISP2_DAT13__FEC_TX_CLK	0x80000000
				MX51_PAD_DISP2_DAT14__FEC_RDATA0	0x80000000
				MX51_PAD_DISP2_DAT15__FEC_TDATA0	0x80000000
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX51_PAD_GPIO1_2__I2C2_SCL		0x400001ed
				MX51_PAD_GPIO1_3__I2C2_SDA		0x400001ed
			>;
		};

		pinctrl_nfc: nfcgrp {
			fsl,pins = <
				MX51_PAD_NANDF_D0__NANDF_D0		0x80000000
				MX51_PAD_NANDF_D1__NANDF_D1		0x80000000
				MX51_PAD_NANDF_D2__NANDF_D2		0x80000000
				MX51_PAD_NANDF_D3__NANDF_D3		0x80000000
				MX51_PAD_NANDF_D4__NANDF_D4		0x80000000
				MX51_PAD_NANDF_D5__NANDF_D5		0x80000000
				MX51_PAD_NANDF_D6__NANDF_D6		0x80000000
				MX51_PAD_NANDF_D7__NANDF_D7		0x80000000
				MX51_PAD_NANDF_ALE__NANDF_ALE		0x80000000
				MX51_PAD_NANDF_CLE__NANDF_CLE		0x80000000
				MX51_PAD_NANDF_RE_B__NANDF_RE_B		0x80000000
				MX51_PAD_NANDF_WE_B__NANDF_WE_B		0x80000000
				MX51_PAD_NANDF_WP_B__NANDF_WP_B		0x80000000
				MX51_PAD_NANDF_CS0__NANDF_CS0		0x80000000
				MX51_PAD_NANDF_RB0__NANDF_RB0		0x80000000
			>;
		};

		pinctrl_lan9221: lan9221grp {
			fsl,pins = <
				MX51_PAD_GPIO1_9__GPIO1_9		0xe5 /* IRQ */
			>;
		};

		pinctrl_mc13892: mc13892grp {
			fsl,pins = <
				MX51_PAD_GPIO1_5__GPIO1_5		0xe5 /* IRQ */
			>;
		};

		pinctrl_mma7455l: mma7455lgrp {
			fsl,pins = <
				MX51_PAD_GPIO1_7__GPIO1_7		0xe5 /* IRQ1 */
				MX51_PAD_GPIO1_6__GPIO1_6		0xe5 /* IRQ2 */
			>;
		};

		pinctrl_weim: weimgrp {
			fsl,pins = <
				MX51_PAD_EIM_DA0__EIM_DA0		0x80000000
				MX51_PAD_EIM_DA1__EIM_DA1		0x80000000
				MX51_PAD_EIM_DA2__EIM_DA2		0x80000000
				MX51_PAD_EIM_DA3__EIM_DA3		0x80000000
				MX51_PAD_EIM_DA4__EIM_DA4		0x80000000
				MX51_PAD_EIM_DA5__EIM_DA5		0x80000000
				MX51_PAD_EIM_DA6__EIM_DA6		0x80000000
				MX51_PAD_EIM_DA7__EIM_DA7		0x80000000
				MX51_PAD_EIM_DA8__EIM_DA8		0x80000000
				MX51_PAD_EIM_DA9__EIM_DA9		0x80000000
				MX51_PAD_EIM_DA10__EIM_DA10		0x80000000
				MX51_PAD_EIM_DA11__EIM_DA11		0x80000000
				MX51_PAD_EIM_DA12__EIM_DA12		0x80000000
				MX51_PAD_EIM_DA13__EIM_DA13		0x80000000
				MX51_PAD_EIM_DA14__EIM_DA14		0x80000000
				MX51_PAD_EIM_DA15__EIM_DA15		0x80000000
				MX51_PAD_EIM_A16__EIM_A16		0x80000000
				MX51_PAD_EIM_A17__EIM_A17		0x80000000
				MX51_PAD_EIM_A18__EIM_A18		0x80000000
				MX51_PAD_EIM_A19__EIM_A19		0x80000000
				MX51_PAD_EIM_A20__EIM_A20		0x80000000
				MX51_PAD_EIM_A21__EIM_A21		0x80000000
				MX51_PAD_EIM_A22__EIM_A22		0x80000000
				MX51_PAD_EIM_A23__EIM_A23		0x80000000
				MX51_PAD_EIM_A24__EIM_A24		0x80000000
				MX51_PAD_EIM_A25__EIM_A25		0x80000000
				MX51_PAD_EIM_A26__EIM_A26		0x80000000
				MX51_PAD_EIM_A27__EIM_A27		0x80000000
				MX51_PAD_EIM_D16__EIM_D16		0x80000000
				MX51_PAD_EIM_D17__EIM_D17		0x80000000
				MX51_PAD_EIM_D18__EIM_D18		0x80000000
				MX51_PAD_EIM_D19__EIM_D19		0x80000000
				MX51_PAD_EIM_D20__EIM_D20		0x80000000
				MX51_PAD_EIM_D21__EIM_D21		0x80000000
				MX51_PAD_EIM_D22__EIM_D22		0x80000000
				MX51_PAD_EIM_D23__EIM_D23		0x80000000
				MX51_PAD_EIM_D24__EIM_D24		0x80000000
				MX51_PAD_EIM_D25__EIM_D25		0x80000000
				MX51_PAD_EIM_D26__EIM_D26		0x80000000
				MX51_PAD_EIM_D27__EIM_D27		0x80000000
				MX51_PAD_EIM_D28__EIM_D28		0x80000000
				MX51_PAD_EIM_D29__EIM_D29		0x80000000
				MX51_PAD_EIM_D30__EIM_D30		0x80000000
				MX51_PAD_EIM_D31__EIM_D31		0x80000000
				MX51_PAD_EIM_OE__EIM_OE			0x80000000
				MX51_PAD_EIM_DTACK__EIM_DTACK		0x80000000
				MX51_PAD_EIM_LBA__EIM_LBA		0x80000000
				MX51_PAD_EIM_CS5__EIM_CS5		0x80000000 /* CS5 */
			>;
		};
	};
};