summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
blob: a031bee311df4e7134c5715f2f4754291a372f9b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
/*
 * Copyright 2017 Armadeus Systems <support@armadeus.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of
 *     the License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
 *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "imx6ul.dtsi"

/ {
	memory@80000000 {
		reg = <0x80000000 0>; /* will be filled by U-Boot */
	};

	reg_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	usdhc3_pwrseq: usdhc3-pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-reset-duration = <1>;
	phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_3v3>;
	status = "okay";

	mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			interrupt-parent = <&gpio4>;
			interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
			status = "okay";
		};
	};
};

/* Bluetooth */
&uart8 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart8>;
	uart-has-rtscts;
	status = "okay";
};

/* eMMC */
&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	no-1-8-v;
	non-removable;
	status = "okay";
};

/* WiFi */
&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	no-1-8-v;
	non-removable;
	mmc-pwrseq = <&usdhc3_pwrseq>;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;

	brcmf: wifi@1 {
		compatible = "brcm,bcm4329-fmac";
		reg = <1>;
		interrupt-parent = <&gpio2>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "host-wake";
	};
};

&iomuxc {
	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x130b0
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x130b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x130b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x130b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			/* INT# */
			MX6UL_PAD_NAND_DQS__GPIO4_IO16		0x1b0b0
			/* RST# */
			MX6UL_PAD_NAND_DATA00__GPIO4_IO02	0x130b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
		>;
	};

	pinctrl_uart8: uart8grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS	0x1b0b0
			/* BT_REG_ON */
			MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10	0x130b0
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
			MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17059
			MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17059
			MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17059
			MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17059
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA18__USDHC2_CMD	0x1b0b0
			MX6UL_PAD_LCD_DATA19__USDHC2_CLK	0x100b0
			MX6UL_PAD_LCD_DATA20__USDHC2_DATA0	0x1b0b0
			MX6UL_PAD_LCD_DATA21__USDHC2_DATA1	0x1b0b0
			MX6UL_PAD_LCD_DATA22__USDHC2_DATA2	0x1b0b0
			MX6UL_PAD_LCD_DATA23__USDHC2_DATA3	0x1b0b0
			/* WL_REG_ON */
			MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09	0x130b0
			/* WL_IRQ */
			MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08	0x1b0b0
		>;
	};
};