summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/imx7-colibri.dtsi
blob: e18e89dec879253930743e8ed23c8d0b8002d6ca (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright 2016-2020 Toradex
 */

/ {
	bl: backlight {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_bl_on>;
		pwms = <&pwm1 0 5000000 0>;
		enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
	};

	reg_module_3v3: regulator-module-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "+V3.3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_module_3v3_avdd: regulator-module-3v3-avdd {
		compatible = "regulator-fixed";
		regulator-name = "+V3.3_AVDD_AUDIO";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "imx7-sgtl5000";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,cpu {
			sound-dai = <&sai1>;
		};

		dailink_master: simple-audio-card,codec {
			sound-dai = <&codec>;
			clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
		};
	};
};

&adc1 {
	vref-supply = <&reg_DCDC3>;
};

&adc2 {
	vref-supply = <&reg_DCDC3>;
};

&cpu0 {
	cpu-supply = <&reg_DCDC2>;
};

&ecspi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
	cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
};

&fec1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_enet1>;
	pinctrl-1 = <&pinctrl_enet1_sleep>;
	clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
		<&clks IMX7D_ENET_AXI_ROOT_CLK>,
		<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
		<&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	assigned-clock-rates = <0>, <100000000>;
	phy-mode = "rmii";
	phy-supply = <&reg_LDO1>;
	fsl,magic-packet;
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "disabled";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	status = "disabled";
};

&gpio1 {
	gpio-line-names = "SODIMM_43",
			  "SODIMM_45",
			  "SODIMM_135",
			  "SODIMM_22",
			  "",
			  "",
			  "SODIMM_37",
			  "SODIMM_29",
			  "SODIMM_59",
			  "SODIMM_28",
			  "SODIMM_30",
			  "SODIMM_67",
			  "",
			  "",
			  "SODIMM_188",
			  "SODIMM_178";
};

&gpio2 {
	gpio-line-names = "SODIMM_111",
			  "SODIMM_113",
			  "SODIMM_115",
			  "SODIMM_117",
			  "SODIMM_119",
			  "SODIMM_121",
			  "SODIMM_123",
			  "SODIMM_125",
			  "SODIMM_91",
			  "SODIMM_89",
			  "SODIMM_105",
			  "SODIMM_152",
			  "SODIMM_150",
			  "SODIMM_95",
			  "SODIMM_126",
			  "SODIMM_107",
			  "SODIMM_114",
			  "SODIMM_116",
			  "SODIMM_118",
			  "SODIMM_120",
			  "SODIMM_122",
			  "SODIMM_124",
			  "SODIMM_127",
			  "SODIMM_130",
			  "SODIMM_132",
			  "SODIMM_134",
			  "SODIMM_133",
			  "SODIMM_104",
			  "SODIMM_106",
			  "SODIMM_110",
			  "SODIMM_112",
			  "SODIMM_128";
};

&gpio3 {
	gpio-line-names = "SODIMM_56",
			  "SODIMM_44",
			  "SODIMM_68",
			  "SODIMM_82",
			  "SODIMM_93",
			  "SODIMM_76",
			  "SODIMM_70",
			  "SODIMM_60",
			  "SODIMM_58",
			  "SODIMM_78",
			  "SODIMM_72",
			  "SODIMM_80",
			  "SODIMM_46",
			  "SODIMM_62",
			  "SODIMM_48",
			  "SODIMM_74",
			  "SODIMM_50",
			  "SODIMM_52",
			  "SODIMM_54",
			  "SODIMM_66",
			  "SODIMM_64",
			  "SODIMM_57",
			  "SODIMM_61",
			  "SODIMM_136",
			  "SODIMM_138",
			  "SODIMM_140",
			  "SODIMM_142",
			  "SODIMM_144",
			  "SODIMM_146";
};

&gpio4 {
	gpio-line-names = "SODIMM_35",
			  "SODIMM_33",
			  "SODIMM_38",
			  "SODIMM_36",
			  "SODIMM_21",
			  "SODIMM_19",
			  "SODIMM_131",
			  "SODIMM_129",
			  "SODIMM_90",
			  "SODIMM_92",
			  "SODIMM_88",
			  "SODIMM_86",
			  "SODIMM_81",
			  "SODIMM_94",
			  "SODIMM_96",
			  "SODIMM_75",
			  "SODIMM_101",
			  "SODIMM_103",
			  "SODIMM_79",
			  "SODIMM_97",
			  "SODIMM_67",
			  "SODIMM_59",
			  "SODIMM_85",
			  "SODIMM_65";
};

&gpio5 {
	gpio-line-names = "SODIMM_69",
			  "SODIMM_71",
			  "SODIMM_73",
			  "SODIMM_47",
			  "SODIMM_190",
			  "SODIMM_192",
			  "SODIMM_49",
			  "SODIMM_51",
			  "SODIMM_53",
			  "",
			  "",
			  "SODIMM_98",
			  "SODIMM_184",
			  "SODIMM_186",
			  "SODIMM_23",
			  "SODIMM_31",
			  "SODIMM_100",
			  "SODIMM_102";
};

&gpio6 {
	gpio-line-names = "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_169",
			  "",
			  "",
			  "",
			  "SODIMM_77",
			  "SODIMM_24",
			  "",
			  "SODIMM_25",
			  "SODIMM_27",
			  "SODIMM_32",
			  "SODIMM_34";
};

&gpio7 {
	gpio-line-names = "",
			  "",
			  "SODIMM_63",
			  "SODIMM_55",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_196",
			  "SODIMM_194",
			  "",
			  "SODIMM_99",
			  "",
			  "",
			  "SODIMM_137";
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	fsl,use-minimum-ecc;
	nand-on-flash-bbt;
	nand-ecc-mode = "hw";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
	pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
	scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	status = "okay";

	codec: sgtl5000@a {
		compatible = "fsl,sgtl5000";
		#sound-dai-cells = <0>;
		reg = <0x0a>;
		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_sai1_mclk>;
		VDDA-supply = <&reg_module_3v3_avdd>;
		VDDIO-supply = <&reg_module_3v3>;
		VDDD-supply = <&reg_DCDC3>;
	};

	ad7879@2c {
		compatible = "adi,ad7879-1";
		reg = <0x2c>;
		interrupt-parent = <&gpio1>;
		interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
		touchscreen-max-pressure = <4096>;
		adi,resistance-plate-x = <120>;
		adi,first-conversion-delay = /bits/ 8 <3>;
		adi,acquisition-time = /bits/ 8 <1>;
		adi,median-filter-size = /bits/ 8 <2>;
		adi,averaging = /bits/ 8 <1>;
		adi,conversion-interval = /bits/ 8 <255>;
	};

	pmic@33 {
		compatible = "ricoh,rn5t567";
		reg = <0x33>;

		regulators {
			reg_DCDC1: DCDC1 {  /* V1.0_SOC */
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1100000>;
				regulator-boot-on;
				regulator-always-on;
			};

			reg_DCDC2: DCDC2 { /* V1.1_ARM */
				regulator-min-microvolt = <975000>;
				regulator-max-microvolt = <1100000>;
				regulator-boot-on;
				regulator-always-on;
			};

			reg_DCDC3: DCDC3 { /* V1.8 */
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			reg_DCDC4: DCDC4 { /* V1.35_DRAM */
				regulator-min-microvolt = <1350000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
			};

			reg_LDO2: LDO2 { /* +V1.8_SD */
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			reg_LDO4: LDO4 { /* V1.8_LPSR */
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_recovery>;
	scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};

&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat
		     &pinctrl_lcdif_ctrl>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
};

&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
};

&reg_1p0d {
	vin-supply = <&reg_DCDC3>;
};

&sai1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
	uart-has-rtscts;
	fsl,dte-mode;
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
	uart-has-rtscts;
	fsl,dte-mode;
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
	fsl,dte-mode;
};

&usbotg1 {
	dr_mode = "host";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
	disable-wp;
	vqmmc-supply = <&reg_LDO2>;
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
	assigned-clock-rates = <400000000>;
	bus-width = <8>;
	fsl,tuning-step = <2>;
	vmmc-supply = <&reg_module_3v3>;
	vqmmc-supply = <&reg_DCDC3>;
	non-removable;
	sdhci-caps-mask = <0x80000000 0x0>;
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4
		     &pinctrl_gpio7 &pinctrl_usbc_det>;

	pinctrl_gpio1: gpio1-grp {
		fsl,pins = <
			MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16	0x14 /* SODIMM 77 */
			MX7D_PAD_EPDC_DATA09__GPIO2_IO9		0x14 /* SODIMM 89 */
			MX7D_PAD_EPDC_DATA08__GPIO2_IO8		0x74 /* SODIMM 91 */
			MX7D_PAD_LCD_RESET__GPIO3_IO4		0x14 /* SODIMM 93 */
			MX7D_PAD_EPDC_DATA13__GPIO2_IO13	0x14 /* SODIMM 95 */
			MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11	0x14 /* SODIMM 99 */
			MX7D_PAD_EPDC_DATA10__GPIO2_IO10	0x74 /* SODIMM 105 */
			MX7D_PAD_EPDC_DATA00__GPIO2_IO0		0x14 /* SODIMM 111 */
			MX7D_PAD_EPDC_DATA01__GPIO2_IO1		0x14 /* SODIMM 113 */
			MX7D_PAD_EPDC_DATA02__GPIO2_IO2		0x14 /* SODIMM 115 */
			MX7D_PAD_EPDC_DATA03__GPIO2_IO3		0x14 /* SODIMM 117 */
			MX7D_PAD_EPDC_DATA04__GPIO2_IO4		0x14 /* SODIMM 119 */
			MX7D_PAD_EPDC_DATA05__GPIO2_IO5		0x14 /* SODIMM 121 */
			MX7D_PAD_EPDC_DATA06__GPIO2_IO6		0x14 /* SODIMM 123 */
			MX7D_PAD_EPDC_DATA07__GPIO2_IO7		0x14 /* SODIMM 125 */
			MX7D_PAD_EPDC_SDCE2__GPIO2_IO22		0x14 /* SODIMM 127 */
			MX7D_PAD_UART3_RTS_B__GPIO4_IO6		0x14 /* SODIMM 131 */
			MX7D_PAD_EPDC_GDRL__GPIO2_IO26		0x14 /* SODIMM 133 */
			MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12	0x14 /* SODIMM 169 */
			MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17	0x14 /* SODIMM 24 */
			MX7D_PAD_SD2_DATA2__GPIO5_IO16		0x14 /* SODIMM 100 */
			MX7D_PAD_SD2_DATA3__GPIO5_IO17		0x14 /* SODIMM 102 */
			MX7D_PAD_EPDC_GDSP__GPIO2_IO27		0x14 /* SODIMM 104 */
			MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x14 /* SODIMM 110 */
			MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30	0x14 /* SODIMM 112 */
			MX7D_PAD_EPDC_SDCLK__GPIO2_IO16		0x14 /* SODIMM 114 */
			MX7D_PAD_EPDC_SDLE__GPIO2_IO17		0x14 /* SODIMM 116 */
			MX7D_PAD_EPDC_SDOE__GPIO2_IO18		0x14 /* SODIMM 118 */
			MX7D_PAD_EPDC_SDSHR__GPIO2_IO19		0x14 /* SODIMM 120 */
			MX7D_PAD_EPDC_SDCE0__GPIO2_IO20		0x14 /* SODIMM 122 */
			MX7D_PAD_EPDC_SDCE1__GPIO2_IO21		0x14 /* SODIMM 124 */
			MX7D_PAD_EPDC_DATA14__GPIO2_IO14	0x14 /* SODIMM 126 */
			MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x14 /* SODIMM 128 */
			MX7D_PAD_EPDC_SDCE3__GPIO2_IO23		0x14 /* SODIMM 130 */
			MX7D_PAD_EPDC_GDCLK__GPIO2_IO24		0x14 /* SODIMM 132 */
			MX7D_PAD_EPDC_GDOE__GPIO2_IO25		0x14 /* SODIMM 134 */
			MX7D_PAD_EPDC_DATA12__GPIO2_IO12	0x14 /* SODIMM 150 */
			MX7D_PAD_EPDC_DATA11__GPIO2_IO11	0x14 /* SODIMM 152 */
			MX7D_PAD_SD2_CLK__GPIO5_IO12		0x14 /* SODIMM 184 */
			MX7D_PAD_SD2_CMD__GPIO5_IO13		0x14 /* SODIMM 186 */
		>;
	};

	pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
		fsl,pins = <
			MX7D_PAD_ECSPI2_SS0__GPIO4_IO23		0x14 /* SODIMM 65 */
			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x74 /* SODIMM 69 */
			MX7D_PAD_I2C4_SDA__GPIO4_IO15		0x14 /* SODIMM 75 */
			MX7D_PAD_ECSPI1_MISO__GPIO4_IO18	0x14 /* SODIMM 79 */
			MX7D_PAD_I2C3_SCL__GPIO4_IO12		0x14 /* SODIMM 81 */
			MX7D_PAD_ECSPI2_MISO__GPIO4_IO22	0x14 /* SODIMM 85 */
			MX7D_PAD_ECSPI1_SS0__GPIO4_IO19		0x14 /* SODIMM 97 */
			MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16	0x14 /* SODIMM 101 */
			MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17	0x14 /* SODIMM 103 */
			MX7D_PAD_I2C3_SDA__GPIO4_IO13		0x14 /* SODIMM 94 */
			MX7D_PAD_I2C4_SCL__GPIO4_IO14		0x14 /* SODIMM 96 */
			MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x14 /* SODIMM 98 */
		>;
	};

	pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */
		fsl,pins = <
			MX7D_PAD_LCD_DATA18__GPIO3_IO23		0x14 /* SODIMM 136 */
			MX7D_PAD_LCD_DATA19__GPIO3_IO24		0x14 /* SODIMM 138 */
			MX7D_PAD_LCD_DATA20__GPIO3_IO25		0x14 /* SODIMM 140 */
			MX7D_PAD_LCD_DATA21__GPIO3_IO26		0x14 /* SODIMM 142 */
			MX7D_PAD_LCD_DATA22__GPIO3_IO27		0x74 /* SODIMM 144 */
			MX7D_PAD_LCD_DATA23__GPIO3_IO28		0x74 /* SODIMM 146 */
		>;
	};

	pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */
		fsl,pins = <
			MX7D_PAD_GPIO1_IO15__GPIO1_IO15		0x14 /* SODIMM 178 */
			MX7D_PAD_GPIO1_IO14__GPIO1_IO14		0x14 /* SODIMM 188 */
		>;
	};

	pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */
		fsl,pins = <
			MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3	0x14 /* SODIMM 55 */
			MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2	0x14 /* SODIMM 63 */
		>;
	};

	pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
		fsl,pins = <
			MX7D_PAD_GPIO1_IO13__GPIO1_IO13	0x79
		>;
	};

	pinctrl_can_int: can-int-grp {
		fsl,pins = <
			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0X14 /* SODIMM 73 */
		>;
	};

	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x73
			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x73
			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x73
			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER		0x73

			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x73
			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x73
			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x73
			MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1		0x73
			MX7D_PAD_SD2_CD_B__ENET1_MDIO			0x3
			MX7D_PAD_SD2_WP__ENET1_MDC			0x3
		>;
	};

	pinctrl_enet1_sleep: enet1sleepgrp {
		fsl,pins = <
			MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4		0x0
			MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0		0x0
			MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1		0x0
			MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5		0x0

			MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10		0x0
			MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6		0x0
			MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7		0x0
			MX7D_PAD_GPIO1_IO12__GPIO1_IO12			0x0
			MX7D_PAD_SD2_CD_B__GPIO5_IO9			0x0
			MX7D_PAD_SD2_WP__GPIO5_IO10			0x0
		>;
	};

	pinctrl_ecspi3_cs: ecspi3-cs-grp {
		fsl,pins = <
			MX7D_PAD_I2C2_SDA__GPIO4_IO11		0x14
		>;
	};

	pinctrl_ecspi3: ecspi3-grp {
		fsl,pins = <
			MX7D_PAD_I2C1_SCL__ECSPI3_MISO		0x2
			MX7D_PAD_I2C1_SDA__ECSPI3_MOSI		0x2
			MX7D_PAD_I2C2_SCL__ECSPI3_SCLK		0x2
		>;
	};

	pinctrl_flexcan1: flexcan1-grp {
		fsl,pins = <
			MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX	0x79 /* SODIMM 55 */
			MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX	0x79 /* SODIMM 63 */
		>;
	};

	pinctrl_flexcan2: flexcan2-grp {
		fsl,pins = <
			MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x79 /* SODIMM 188 */
			MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x79 /* SODIMM 178 */
		>;
	};

	pinctrl_gpio_bl_on: gpio-bl-on {
		fsl,pins = <
			MX7D_PAD_SD1_WP__GPIO5_IO1		0x14 /* SODIMM 71 */
		>;
	};

	pinctrl_gpmi_nand: gpmi-nand-grp {
		fsl,pins = <
			MX7D_PAD_SD3_CLK__NAND_CLE		0x71
			MX7D_PAD_SD3_CMD__NAND_ALE		0x71
			MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	0x71
			MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	0x74
			MX7D_PAD_SD3_STROBE__NAND_RE_B		0x71
			MX7D_PAD_SD3_RESET_B__NAND_WE_B		0x71
			MX7D_PAD_SD3_DATA0__NAND_DATA00		0x71
			MX7D_PAD_SD3_DATA1__NAND_DATA01		0x71
			MX7D_PAD_SD3_DATA2__NAND_DATA02		0x71
			MX7D_PAD_SD3_DATA3__NAND_DATA03		0x71
			MX7D_PAD_SD3_DATA4__NAND_DATA04		0x71
			MX7D_PAD_SD3_DATA5__NAND_DATA05		0x71
			MX7D_PAD_SD3_DATA6__NAND_DATA06		0x71
			MX7D_PAD_SD3_DATA7__NAND_DATA07		0x71
		>;
	};

	pinctrl_i2c4: i2c4-grp {
		fsl,pins = <
			MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA	0x4000007f
			MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL	0x4000007f
		>;
	};

	pinctrl_i2c4_recovery: i2c4-recoverygrp {
		fsl,pins = <
			MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8	0x4000007f
			MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9	0x4000007f
		>;
	};

	pinctrl_lcdif_dat: lcdif-dat-grp {
		fsl,pins = <
			MX7D_PAD_LCD_DATA00__LCD_DATA0		0x79
			MX7D_PAD_LCD_DATA01__LCD_DATA1		0x79
			MX7D_PAD_LCD_DATA02__LCD_DATA2		0x79
			MX7D_PAD_LCD_DATA03__LCD_DATA3		0x79
			MX7D_PAD_LCD_DATA04__LCD_DATA4		0x79
			MX7D_PAD_LCD_DATA05__LCD_DATA5		0x79
			MX7D_PAD_LCD_DATA06__LCD_DATA6		0x79
			MX7D_PAD_LCD_DATA07__LCD_DATA7		0x79
			MX7D_PAD_LCD_DATA08__LCD_DATA8		0x79
			MX7D_PAD_LCD_DATA09__LCD_DATA9		0x79
			MX7D_PAD_LCD_DATA10__LCD_DATA10		0x79
			MX7D_PAD_LCD_DATA11__LCD_DATA11		0x79
			MX7D_PAD_LCD_DATA12__LCD_DATA12		0x79
			MX7D_PAD_LCD_DATA13__LCD_DATA13		0x79
			MX7D_PAD_LCD_DATA14__LCD_DATA14		0x79
			MX7D_PAD_LCD_DATA15__LCD_DATA15		0x79
			MX7D_PAD_LCD_DATA16__LCD_DATA16		0x79
			MX7D_PAD_LCD_DATA17__LCD_DATA17		0x79
		>;
	};

	pinctrl_lcdif_dat_24: lcdif-dat-24-grp {
		fsl,pins = <
			MX7D_PAD_LCD_DATA18__LCD_DATA18		0x79
			MX7D_PAD_LCD_DATA19__LCD_DATA19		0x79
			MX7D_PAD_LCD_DATA20__LCD_DATA20		0x79
			MX7D_PAD_LCD_DATA21__LCD_DATA21		0x79
			MX7D_PAD_LCD_DATA22__LCD_DATA22		0x79
			MX7D_PAD_LCD_DATA23__LCD_DATA23		0x79
		>;
	};

	pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
		fsl,pins = <
			MX7D_PAD_LCD_CLK__LCD_CLK		0x79
			MX7D_PAD_LCD_ENABLE__LCD_ENABLE		0x79
			MX7D_PAD_LCD_VSYNC__LCD_VSYNC		0x79
			MX7D_PAD_LCD_HSYNC__LCD_HSYNC		0x79
		>;
	};

	pinctrl_pwm1: pwm1-grp {
		fsl,pins = <
			MX7D_PAD_GPIO1_IO08__PWM1_OUT		0x79
			MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21	0x4
		>;
	};

	pinctrl_pwm2: pwm2-grp {
		fsl,pins = <
			MX7D_PAD_GPIO1_IO09__PWM2_OUT		0x79
		>;
	};

	pinctrl_pwm3: pwm3-grp {
		fsl,pins = <
			MX7D_PAD_GPIO1_IO10__PWM3_OUT		0x79
		>;
	};

	pinctrl_pwm4: pwm4-grp {
		fsl,pins = <
			MX7D_PAD_GPIO1_IO11__PWM4_OUT		0x79
			MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20	0x4
		>;
	};

	pinctrl_uart1: uart1-grp {
		fsl,pins = <
			MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX	0x79
			MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX	0x79
			MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS	0x79
			MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS	0x79
		>;
	};

	pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
		fsl,pins = <
			MX7D_PAD_SD2_DATA1__GPIO5_IO15		0x14 /* DCD */
			MX7D_PAD_SD2_DATA0__GPIO5_IO14		0x14 /* DTR */
		>;
	};

	pinctrl_uart2: uart2-grp {
		fsl,pins = <
			MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79
			MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79
			MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79
			MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79
		>;
	};
	pinctrl_uart3: uart3-grp {
		fsl,pins = <
			MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
			MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
		>;
	};

	pinctrl_usbc_det: gpio-usbc-det {
		fsl,pins = <
			MX7D_PAD_ENET1_CRS__GPIO7_IO14	0x14
		>;
	};

	pinctrl_usbh_reg: gpio-usbh-vbus {
		fsl,pins = <
			MX7D_PAD_UART3_CTS_B__GPIO4_IO7	0x14 /* SODIMM 129 USBH PEN */
		>;
	};

	pinctrl_usdhc1: usdhc1-grp {
		fsl,pins = <
			MX7D_PAD_SD1_CMD__SD1_CMD	0x59
			MX7D_PAD_SD1_CLK__SD1_CLK	0x19
			MX7D_PAD_SD1_DATA0__SD1_DATA0	0x59
			MX7D_PAD_SD1_DATA1__SD1_DATA1	0x59
			MX7D_PAD_SD1_DATA2__SD1_DATA2	0x59
			MX7D_PAD_SD1_DATA3__SD1_DATA3	0x59
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
		fsl,pins = <
			MX7D_PAD_SD1_CMD__SD1_CMD	0x5a
			MX7D_PAD_SD1_CLK__SD1_CLK	0x1a
			MX7D_PAD_SD1_DATA0__SD1_DATA0	0x5a
			MX7D_PAD_SD1_DATA1__SD1_DATA1	0x5a
			MX7D_PAD_SD1_DATA2__SD1_DATA2	0x5a
			MX7D_PAD_SD1_DATA3__SD1_DATA3	0x5a
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
		fsl,pins = <
			MX7D_PAD_SD1_CMD__SD1_CMD	0x5b
			MX7D_PAD_SD1_CLK__SD1_CLK	0x1b
			MX7D_PAD_SD1_DATA0__SD1_DATA0	0x5b
			MX7D_PAD_SD1_DATA1__SD1_DATA1	0x5b
			MX7D_PAD_SD1_DATA2__SD1_DATA2	0x5b
			MX7D_PAD_SD1_DATA3__SD1_DATA3	0x5b
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
			MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
		fsl,pins = <
			MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
			MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
			MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
		fsl,pins = <
			MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
			MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
			MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
		>;
	};

	pinctrl_sai1: sai1-grp {
		fsl,pins = <
			MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
			MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC	0x1f
			MX7D_PAD_ENET1_COL__SAI1_TX_DATA0	0x30
			MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0	0x1f
		>;
	};

	pinctrl_sai1_mclk: sai1grp_mclk {
		fsl,pins = <
			MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
		>;
	};
};

&iomuxc_lpsr {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_lpsr>;

	pinctrl_gpio_lpsr: gpio1-grp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2	0x59
			MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3	0x59
		>;
	};

	pinctrl_gpiokeys: gpiokeysgrp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1	0x19
		>;
	};

	pinctrl_i2c1: i2c1-grp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA	0x4000007f
			MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL	0x4000007f
		>;
	};

	pinctrl_i2c1_recovery: i2c1-recoverygrp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4	0x4000007f
			MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x4000007f
		>;
	};

	pinctrl_cd_usdhc1: usdhc1-cd-grp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0	0x59 /* CD */
		>;
	};

	pinctrl_uart1_ctrl2: uart1-ctrl2-grp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	0x14 /* DSR */
			MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6	0x14 /* RI */
		>;
	};
};