summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/r8a7791.dtsi
blob: 0d82a4b3c650cf197c107a88a7d962378cf94e16 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
/*
 * Device Tree Source for the r8a7791 SoC
 *
 * Copyright (C) 2013 Renesas Electronics Corporation
 * Copyright (C) 2013-2014 Renesas Solutions Corp.
 * Copyright (C) 2014 Cogent Embedded Inc.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/clock/r8a7791-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r8a7791";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		i2c7 = &i2c7;
		i2c8 = &i2c8;
		spi0 = &qspi;
		spi1 = &msiof0;
		spi2 = &msiof1;
		spi3 = &msiof2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			clock-frequency = <1500000000>;
			voltage-tolerance = <1>; /* 1% */
			clocks = <&cpg_clocks R8A7791_CLK_Z>;
			clock-latency = <300000>; /* 300 us */

			/* kHz - uV - OPPs unknown yet */
			operating-points = <1500000 1000000>,
					   <1312500 1000000>,
					   <1125000 1000000>,
					   < 937500 1000000>,
					   < 750000 1000000>,
					   < 375000 1000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
			clock-frequency = <1500000000>;
		};
	};

	gic: interrupt-controller@f1001000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0xf1001000 0 0x1000>,
			<0 0xf1002000 0 0x1000>,
			<0 0xf1004000 0 0x2000>,
			<0 0xf1006000 0 0x2000>;
		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	gpio0: gpio@e6050000 {
		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
		reg = <0 0xe6050000 0 0x50>;
		interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
	};

	gpio1: gpio@e6051000 {
		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
		reg = <0 0xe6051000 0 0x50>;
		interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
	};

	gpio2: gpio@e6052000 {
		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
		reg = <0 0xe6052000 0 0x50>;
		interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
	};

	gpio3: gpio@e6053000 {
		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
		reg = <0 0xe6053000 0 0x50>;
		interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
	};

	gpio4: gpio@e6054000 {
		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
		reg = <0 0xe6054000 0 0x50>;
		interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
	};

	gpio5: gpio@e6055000 {
		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
		reg = <0 0xe6055000 0 0x50>;
		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 160 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
	};

	gpio6: gpio@e6055400 {
		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
		reg = <0 0xe6055400 0 0x50>;
		interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 192 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
	};

	gpio7: gpio@e6055800 {
		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
		reg = <0 0xe6055800 0 0x50>;
		interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 224 26>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
	};

	thermal@e61f0000 {
		compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	irqc0: interrupt-controller@e61c0000 {
		compatible = "renesas,irqc-r8a7791", "renesas,irqc";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0 0xe61c0000 0 0x200>;
		interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
			     <0 1 IRQ_TYPE_LEVEL_HIGH>,
			     <0 2 IRQ_TYPE_LEVEL_HIGH>,
			     <0 3 IRQ_TYPE_LEVEL_HIGH>,
			     <0 12 IRQ_TYPE_LEVEL_HIGH>,
			     <0 13 IRQ_TYPE_LEVEL_HIGH>,
			     <0 14 IRQ_TYPE_LEVEL_HIGH>,
			     <0 15 IRQ_TYPE_LEVEL_HIGH>,
			     <0 16 IRQ_TYPE_LEVEL_HIGH>,
			     <0 17 IRQ_TYPE_LEVEL_HIGH>;
	};

	/* The memory map in the User's Manual maps the cores to bus numbers */
	i2c0: i2c@e6508000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7791";
		reg = <0 0xe6508000 0 0x40>;
		interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
		status = "disabled";
	};

	i2c1: i2c@e6518000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7791";
		reg = <0 0xe6518000 0 0x40>;
		interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
		status = "disabled";
	};

	i2c2: i2c@e6530000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7791";
		reg = <0 0xe6530000 0 0x40>;
		interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
		status = "disabled";
	};

	i2c3: i2c@e6540000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7791";
		reg = <0 0xe6540000 0 0x40>;
		interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
		status = "disabled";
	};

	i2c4: i2c@e6520000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7791";
		reg = <0 0xe6520000 0 0x40>;
		interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
		status = "disabled";
	};

	i2c5: i2c@e6528000 {
		/* doesn't need pinmux */
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7791";
		reg = <0 0xe6528000 0 0x40>;
		interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
		status = "disabled";
	};

	i2c6: i2c@e60b0000 {
		/* doesn't need pinmux */
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
		reg = <0 0xe60b0000 0 0x425>;
		interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
		status = "disabled";
	};

	i2c7: i2c@e6500000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
		reg = <0 0xe6500000 0 0x425>;
		interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
		status = "disabled";
	};

	i2c8: i2c@e6510000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
		reg = <0 0xe6510000 0 0x425>;
		interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
		status = "disabled";
	};

	pfc: pfc@e6060000 {
		compatible = "renesas,pfc-r8a7791";
		reg = <0 0xe6060000 0 0x250>;
		#gpio-range-cells = <3>;
	};

	sdhi0: sd@ee100000 {
		compatible = "renesas,sdhi-r8a7791";
		reg = <0 0xee100000 0 0x200>;
		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
		status = "disabled";
	};

	sdhi1: sd@ee140000 {
		compatible = "renesas,sdhi-r8a7791";
		reg = <0 0xee140000 0 0x100>;
		interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
		status = "disabled";
	};

	sdhi2: sd@ee160000 {
		compatible = "renesas,sdhi-r8a7791";
		reg = <0 0xee160000 0 0x100>;
		interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
		status = "disabled";
	};

	scifa0: serial@e6c40000 {
		compatible = "renesas,scifa-r8a7791", "renesas,scifa";
		reg = <0 0xe6c40000 0 64>;
		interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scifa1: serial@e6c50000 {
		compatible = "renesas,scifa-r8a7791", "renesas,scifa";
		reg = <0 0xe6c50000 0 64>;
		interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scifa2: serial@e6c60000 {
		compatible = "renesas,scifa-r8a7791", "renesas,scifa";
		reg = <0 0xe6c60000 0 64>;
		interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scifa3: serial@e6c70000 {
		compatible = "renesas,scifa-r8a7791", "renesas,scifa";
		reg = <0 0xe6c70000 0 64>;
		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scifa4: serial@e6c78000 {
		compatible = "renesas,scifa-r8a7791", "renesas,scifa";
		reg = <0 0xe6c78000 0 64>;
		interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scifa5: serial@e6c80000 {
		compatible = "renesas,scifa-r8a7791", "renesas,scifa";
		reg = <0 0xe6c80000 0 64>;
		interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scifb0: serial@e6c20000 {
		compatible = "renesas,scifb-r8a7791", "renesas,scifb";
		reg = <0 0xe6c20000 0 64>;
		interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scifb1: serial@e6c30000 {
		compatible = "renesas,scifb-r8a7791", "renesas,scifb";
		reg = <0 0xe6c30000 0 64>;
		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scifb2: serial@e6ce0000 {
		compatible = "renesas,scifb-r8a7791", "renesas,scifb";
		reg = <0 0xe6ce0000 0 64>;
		interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scif0: serial@e6e60000 {
		compatible = "renesas,scif-r8a7791", "renesas,scif";
		reg = <0 0xe6e60000 0 64>;
		interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scif1: serial@e6e68000 {
		compatible = "renesas,scif-r8a7791", "renesas,scif";
		reg = <0 0xe6e68000 0 64>;
		interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scif2: serial@e6e58000 {
		compatible = "renesas,scif-r8a7791", "renesas,scif";
		reg = <0 0xe6e58000 0 64>;
		interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scif3: serial@e6ea8000 {
		compatible = "renesas,scif-r8a7791", "renesas,scif";
		reg = <0 0xe6ea8000 0 64>;
		interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scif4: serial@e6ee0000 {
		compatible = "renesas,scif-r8a7791", "renesas,scif";
		reg = <0 0xe6ee0000 0 64>;
		interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scif5: serial@e6ee8000 {
		compatible = "renesas,scif-r8a7791", "renesas,scif";
		reg = <0 0xe6ee8000 0 64>;
		interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	hscif0: serial@e62c0000 {
		compatible = "renesas,hscif-r8a7791", "renesas,hscif";
		reg = <0 0xe62c0000 0 96>;
		interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	hscif1: serial@e62c8000 {
		compatible = "renesas,hscif-r8a7791", "renesas,hscif";
		reg = <0 0xe62c8000 0 96>;
		interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	hscif2: serial@e62d0000 {
		compatible = "renesas,hscif-r8a7791", "renesas,hscif";
		reg = <0 0xe62d0000 0 96>;
		interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	ether: ethernet@ee700000 {
		compatible = "renesas,ether-r8a7791";
		reg = <0 0xee700000 0 0x400>;
		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
		phy-mode = "rmii";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	sata0: sata@ee300000 {
		compatible = "renesas,sata-r8a7791";
		reg = <0 0xee300000 0 0x2000>;
		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
		status = "disabled";
	};

	sata1: sata@ee500000 {
		compatible = "renesas,sata-r8a7791";
		reg = <0 0xee500000 0 0x2000>;
		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
		status = "disabled";
	};

	clocks {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* External root clock */
		extal_clk: extal_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overriden by the board. */
			clock-frequency = <0>;
			clock-output-names = "extal";
		};

		/*
		 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
		 * default. Boards that provide audio clocks should override them.
		 */
		audio_clk_a: audio_clk_a {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "audio_clk_a";
		};
		audio_clk_b: audio_clk_b {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "audio_clk_b";
		};
		audio_clk_c: audio_clk_c {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "audio_clk_c";
		};

		/* External PCIe clock - can be overridden by the board */
		pcie_bus_clk: pcie_bus_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <100000000>;
			clock-output-names = "pcie_bus";
			status = "disabled";
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@e6150000 {
			compatible = "renesas,r8a7791-cpg-clocks",
				     "renesas,rcar-gen2-cpg-clocks";
			reg = <0 0xe6150000 0 0x1000>;
			clocks = <&extal_clk>;
			#clock-cells = <1>;
			clock-output-names = "main", "pll0", "pll1", "pll3",
					     "lb", "qspi", "sdh", "sd0", "z";
		};

		/* Variable factor clocks */
		sd1_clk: sd2_clk@e6150078 {
			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150078 0 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "sd1";
		};
		sd2_clk: sd3_clk@e615026c {
			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe615026c 0 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "sd2";
		};
		mmc0_clk: mmc0_clk@e6150240 {
			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150240 0 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "mmc0";
		};
		ssp_clk: ssp_clk@e6150248 {
			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150248 0 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "ssp";
		};
		ssprs_clk: ssprs_clk@e615024c {
			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe615024c 0 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "ssprs";
		};

		/* Fixed factor clocks */
		pll1_div2_clk: pll1_div2_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "pll1_div2";
		};
		zg_clk: zg_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <3>;
			clock-mult = <1>;
			clock-output-names = "zg";
		};
		zx_clk: zx_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <3>;
			clock-mult = <1>;
			clock-output-names = "zx";
		};
		zs_clk: zs_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <6>;
			clock-mult = <1>;
			clock-output-names = "zs";
		};
		hp_clk: hp_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <12>;
			clock-mult = <1>;
			clock-output-names = "hp";
		};
		i_clk: i_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "i";
		};
		b_clk: b_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <12>;
			clock-mult = <1>;
			clock-output-names = "b";
		};
		p_clk: p_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <24>;
			clock-mult = <1>;
			clock-output-names = "p";
		};
		cl_clk: cl_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <48>;
			clock-mult = <1>;
			clock-output-names = "cl";
		};
		m2_clk: m2_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
			clock-output-names = "m2";
		};
		imp_clk: imp_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <4>;
			clock-mult = <1>;
			clock-output-names = "imp";
		};
		rclk_clk: rclk_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <(48 * 1024)>;
			clock-mult = <1>;
			clock-output-names = "rclk";
		};
		oscclk_clk: oscclk_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <(12 * 1024)>;
			clock-mult = <1>;
			clock-output-names = "oscclk";
		};
		zb3_clk: zb3_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
			#clock-cells = <0>;
			clock-div = <4>;
			clock-mult = <1>;
			clock-output-names = "zb3";
		};
		zb3d2_clk: zb3d2_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
			clock-output-names = "zb3d2";
		};
		ddr_clk: ddr_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
			clock-output-names = "ddr";
		};
		mp_clk: mp_clk {
			compatible = "fixed-factor-clock";
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-div = <15>;
			clock-mult = <1>;
			clock-output-names = "mp";
		};
		cp_clk: cp_clk {
			compatible = "fixed-factor-clock";
			clocks = <&extal_clk>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "cp";
		};

		/* Gate clocks */
		mstp0_clks: mstp0_clks@e6150130 {
			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
			clocks = <&mp_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
			clock-output-names = "msiof0";
		};
		mstp1_clks: mstp1_clks@e6150134 {
			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
			clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
				 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
				R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
				R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
			>;
			clock-output-names =
				"tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
				"vsp1-du0", "vsp1-sy";
		};
		mstp2_clks: mstp2_clks@e6150138 {
			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
				 <&mp_clk>, <&mp_clk>, <&mp_clk>,
				 <&zs_clk>, <&zs_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
				R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
				R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
				R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
			>;
			clock-output-names =
				"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
				"scifb1", "msiof1", "scifb2",
				"sys-dmac1", "sys-dmac0";
		};
		mstp3_clks: mstp3_clks@e615013c {
			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
			clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
				 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
				R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
				R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
			>;
			clock-output-names =
				"tpu0", "sdhi2", "sdhi1", "sdhi0",
				"mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1";
		};
		mstp5_clks: mstp5_clks@e6150144 {
			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
			clocks = <&extal_clk>, <&p_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
			clock-output-names = "thermal", "pwm";
		};
		mstp7_clks: mstp7_clks@e615014c {
			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
			clocks = <&mp_clk>,  <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
				 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
				 <&zx_clk>, <&zx_clk>, <&zx_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
				R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
				R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
				R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
				R8A7791_CLK_LVDS0
			>;
			clock-output-names =
				"ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
				"scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
		};
		mstp8_clks: mstp8_clks@e6150990 {
			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
			clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
				 <&zs_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
				R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
			>;
			clock-output-names =
				"vin2", "vin1", "vin0", "ether", "sata1", "sata0";
		};
		mstp9_clks: mstp9_clks@e6150994 {
			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
			clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
				 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
				 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
				 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
				 <&hp_clk>, <&hp_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
				R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
				R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
				R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
				R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
			>;
			clock-output-names =
				"gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
				"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
				"i2c1", "i2c0";
		};
		mstp10_clks: mstp10_clks@e6150998 {
			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
			clocks = <&p_clk>,
				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
				<&p_clk>,
				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;

			#clock-cells = <1>;
			clock-indices = <
				R8A7791_CLK_SSI_ALL
				R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
				R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
				R8A7791_CLK_SCU_ALL
				R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
				R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
				R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
			>;
			clock-output-names =
				"ssi-all",
				"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
				"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
				"scu-all",
				"scu-dvc1", "scu-dvc0",
				"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
				"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
		};
		mstp11_clks: mstp11_clks@e615099c {
			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
			>;
			clock-output-names = "scifa3", "scifa4", "scifa5";
		};
	};

	qspi: spi@e6b10000 {
		compatible = "renesas,qspi-r8a7791", "renesas,qspi";
		reg = <0 0xe6b10000 0 0x2c>;
		interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
		num-cs = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	msiof0: spi@e6e20000 {
		compatible = "renesas,msiof-r8a7791";
		reg = <0 0xe6e20000 0 0x0064>;
		interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	msiof1: spi@e6e10000 {
		compatible = "renesas,msiof-r8a7791";
		reg = <0 0xe6e10000 0 0x0064>;
		interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	msiof2: spi@e6e00000 {
		compatible = "renesas,msiof-r8a7791";
		reg = <0 0xe6e00000 0 0x0064>;
		interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	pci0: pci@ee090000 {
		compatible = "renesas,pci-r8a7791";
		device_type = "pci";
		clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
		reg = <0 0xee090000 0 0xc00>,
		      <0 0xee080000 0 0x1100>;
		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";

		bus-range = <0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
		interrupt-map-mask = <0xff00 0 0 0x7>;
		interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
				 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
				 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
	};

	pci1: pci@ee0d0000 {
		compatible = "renesas,pci-r8a7791";
		device_type = "pci";
		clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
		reg = <0 0xee0d0000 0 0xc00>,
		      <0 0xee0c0000 0 0x1100>;
		interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";

		bus-range = <1 1>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
		interrupt-map-mask = <0xff00 0 0 0x7>;
		interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
				 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
				 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
	};

	pciec: pcie@fe000000 {
		compatible = "renesas,pcie-r8a7791";
		reg = <0 0xfe000000 0 0x80000>;
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x00 0xff>;
		device_type = "pci";
		ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
			  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
			  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
			  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
		/* Map all possible DDR as inbound ranges */
		dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
			      0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
		interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
			     <0 117 IRQ_TYPE_LEVEL_HIGH>,
			     <0 118 IRQ_TYPE_LEVEL_HIGH>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
		clock-names = "pcie", "pcie_bus";
		status = "disabled";
	};

	rcar_sound: rcar_sound@0xec500000 {
		#sound-dai-cells = <1>;
		compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
		interrupt-parent = <&gic>;
		reg =	<0 0xec500000 0 0x1000>, /* SCU */
			<0 0xec5a0000 0 0x100>,  /* ADG */
			<0 0xec540000 0 0x1000>, /* SSIU */
			<0 0xec541000 0 0x1280>; /* SSI */
		clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
			<&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
			<&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
			<&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
			<&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
			<&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
			<&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
			<&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
			<&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
			<&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
			<&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
			<&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
			<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
		clock-names = "ssi-all",
				"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
				"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
				"src.9", "src.8", "src.7", "src.6", "src.5",
				"src.4", "src.3", "src.2", "src.1", "src.0",
				"dvc.0", "dvc.1",
				"clk_a", "clk_b", "clk_c", "clk_i";

		status = "disabled";

		rcar_sound,dvc {
			dvc0: dvc@0 { };
			dvc1: dvc@1 { };
		};

		rcar_sound,src {
			src0: src@0 { };
			src1: src@1 { };
			src2: src@2 { };
			src3: src@3 { };
			src4: src@4 { };
			src5: src@5 { };
			src6: src@6 { };
			src7: src@7 { };
			src8: src@8 { };
			src9: src@9 { };
		};

		rcar_sound,ssi {
			ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
			ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
			ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
			ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
			ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
			ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
			ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
			ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
			ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
			ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
		};
	};
};