summaryrefslogtreecommitdiff
path: root/arch/arm/mach-omap2/clockdomains44xx_data.c
blob: 8285be7c1eabb00dbddb6d22b3fdb45892d87db7 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP4 Clock domains framework
 *
 * Copyright (C) 2009-2011 Texas Instruments, Inc.
 * Copyright (C) 2009-2011 Nokia Corporation
 *
 * Abhijit Pagare (abhijitpagare@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 * Paul Walmsley (paul@pwsan.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#include <linux/kernel.h>
#include <linux/io.h>

#include "clockdomain.h"
#include "cm1_44xx.h"
#include "cm2_44xx.h"

#include "cm-regbits-44xx.h"
#include "prm44xx.h"
#include "prcm44xx.h"
#include "prcm_mpu44xx.h"

/* Static Dependencies for OMAP4 Clock Domains */

static struct clkdm_dep d2d_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_2_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ .clkdm_name = "l3_init_clkdm" },
	{ .clkdm_name = "l4_cfg_clkdm" },
	{ .clkdm_name = "l4_per_clkdm" },
	{ NULL },
};

static struct clkdm_dep ducati_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_2_clkdm" },
	{ .clkdm_name = "l3_dss_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ .clkdm_name = "l3_gfx_clkdm" },
	{ .clkdm_name = "l3_init_clkdm" },
	{ .clkdm_name = "l4_cfg_clkdm" },
	{ .clkdm_name = "l4_per_clkdm" },
	{ .clkdm_name = "l4_secure_clkdm" },
	{ .clkdm_name = "l4_wkup_clkdm" },
	{ .clkdm_name = "tesla_clkdm" },
	{ NULL },
};

static struct clkdm_dep iss_wkup_sleep_deps[] = {
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ NULL },
};

static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ NULL },
};

static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "ducati_clkdm" },
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_dss_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ .clkdm_name = "l3_init_clkdm" },
	{ .clkdm_name = "l4_cfg_clkdm" },
	{ .clkdm_name = "l4_per_clkdm" },
	{ .clkdm_name = "l4_secure_clkdm" },
	{ .clkdm_name = "l4_wkup_clkdm" },
	{ NULL },
};

static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_2_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ NULL },
};

static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ NULL },
};

static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ .clkdm_name = "l4_cfg_clkdm" },
	{ .clkdm_name = "l4_per_clkdm" },
	{ .clkdm_name = "l4_secure_clkdm" },
	{ .clkdm_name = "l4_wkup_clkdm" },
	{ NULL },
};

static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ .clkdm_name = "l4_per_clkdm" },
	{ NULL },
};

static struct clkdm_dep mpu_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "ducati_clkdm" },
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_2_clkdm" },
	{ .clkdm_name = "l3_dss_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ .clkdm_name = "l3_gfx_clkdm" },
	{ .clkdm_name = "l3_init_clkdm" },
	{ .clkdm_name = "l4_cfg_clkdm" },
	{ .clkdm_name = "l4_per_clkdm" },
	{ .clkdm_name = "l4_secure_clkdm" },
	{ .clkdm_name = "l4_wkup_clkdm" },
	{ .clkdm_name = "tesla_clkdm" },
	{ NULL },
};

static struct clkdm_dep tesla_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_2_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ .clkdm_name = "l3_init_clkdm" },
	{ .clkdm_name = "l4_cfg_clkdm" },
	{ .clkdm_name = "l4_per_clkdm" },
	{ .clkdm_name = "l4_wkup_clkdm" },
	{ NULL },
};

static struct clockdomain l4_cefuse_44xx_clkdm = {
	.name		  = "l4_cefuse_clkdm",
	.pwrdm		  = { .name = "cefuse_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_CEFUSE_INST,
	.clkdm_offs	  = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain l4_cfg_44xx_clkdm = {
	.name		  = "l4_cfg_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_CORE_INST,
	.clkdm_offs	  = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
	.dep_bit	  = OMAP4430_L4CFG_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP,
};

static struct clockdomain tesla_44xx_clkdm = {
	.name		  = "tesla_clkdm",
	.pwrdm		  = { .name = "tesla_pwrdm" },
	.prcm_partition	  = OMAP4430_CM1_PARTITION,
	.cm_inst	  = OMAP4430_CM1_TESLA_INST,
	.clkdm_offs	  = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
	.dep_bit	  = OMAP4430_TESLA_STATDEP_SHIFT,
	.wkdep_srcs	  = tesla_wkup_sleep_deps,
	.sleepdep_srcs	  = tesla_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain l3_gfx_44xx_clkdm = {
	.name		  = "l3_gfx_clkdm",
	.pwrdm		  = { .name = "gfx_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_GFX_INST,
	.clkdm_offs	  = OMAP4430_CM2_GFX_GFX_CDOFFS,
	.dep_bit	  = OMAP4430_GFX_STATDEP_SHIFT,
	.wkdep_srcs	  = l3_gfx_wkup_sleep_deps,
	.sleepdep_srcs	  = l3_gfx_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain ivahd_44xx_clkdm = {
	.name		  = "ivahd_clkdm",
	.pwrdm		  = { .name = "ivahd_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_IVAHD_INST,
	.clkdm_offs	  = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
	.dep_bit	  = OMAP4430_IVAHD_STATDEP_SHIFT,
	.wkdep_srcs	  = ivahd_wkup_sleep_deps,
	.sleepdep_srcs	  = ivahd_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain l4_secure_44xx_clkdm = {
	.name		  = "l4_secure_clkdm",
	.pwrdm		  = { .name = "l4per_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_L4PER_INST,
	.clkdm_offs	  = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
	.dep_bit	  = OMAP4430_L4SEC_STATDEP_SHIFT,
	.wkdep_srcs	  = l4_secure_wkup_sleep_deps,
	.sleepdep_srcs	  = l4_secure_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_SWSUP,
};

static struct clockdomain l4_per_44xx_clkdm = {
	.name		  = "l4_per_clkdm",
	.pwrdm		  = { .name = "l4per_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_L4PER_INST,
	.clkdm_offs	  = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
	.dep_bit	  = OMAP4430_L4PER_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain abe_44xx_clkdm = {
	.name		  = "abe_clkdm",
	.pwrdm		  = { .name = "abe_pwrdm" },
	.prcm_partition	  = OMAP4430_CM1_PARTITION,
	.cm_inst	  = OMAP4430_CM1_ABE_INST,
	.clkdm_offs	  = OMAP4430_CM1_ABE_ABE_CDOFFS,
	.dep_bit	  = OMAP4430_ABE_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain l3_instr_44xx_clkdm = {
	.name		  = "l3_instr_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_CORE_INST,
	.clkdm_offs	  = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
};

static struct clockdomain l3_init_44xx_clkdm = {
	.name		  = "l3_init_clkdm",
	.pwrdm		  = { .name = "l3init_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_L3INIT_INST,
	.clkdm_offs	  = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
	.dep_bit	  = OMAP4430_L3INIT_STATDEP_SHIFT,
	.wkdep_srcs	  = l3_init_wkup_sleep_deps,
	.sleepdep_srcs	  = l3_init_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain d2d_44xx_clkdm = {
	.name		  = "d2d_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_CORE_INST,
	.clkdm_offs	  = OMAP4430_CM2_CORE_D2D_CDOFFS,
	.wkdep_srcs	  = d2d_wkup_sleep_deps,
	.sleepdep_srcs	  = d2d_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain mpu0_44xx_clkdm = {
	.name		  = "mpu0_clkdm",
	.pwrdm		  = { .name = "cpu0_pwrdm" },
	.prcm_partition	  = OMAP4430_PRCM_MPU_PARTITION,
	.cm_inst	  = OMAP4430_PRCM_MPU_CPU0_INST,
	.clkdm_offs	  = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain mpu1_44xx_clkdm = {
	.name		  = "mpu1_clkdm",
	.pwrdm		  = { .name = "cpu1_pwrdm" },
	.prcm_partition	  = OMAP4430_PRCM_MPU_PARTITION,
	.cm_inst	  = OMAP4430_PRCM_MPU_CPU1_INST,
	.clkdm_offs	  = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain l3_emif_44xx_clkdm = {
	.name		  = "l3_emif_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_CORE_INST,
	.clkdm_offs	  = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
	.dep_bit	  = OMAP4430_MEMIF_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain l4_ao_44xx_clkdm = {
	.name		  = "l4_ao_clkdm",
	.pwrdm		  = { .name = "always_on_core_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_ALWAYS_ON_INST,
	.clkdm_offs	  = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain ducati_44xx_clkdm = {
	.name		  = "ducati_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_CORE_INST,
	.clkdm_offs	  = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
	.dep_bit	  = OMAP4430_DUCATI_STATDEP_SHIFT,
	.wkdep_srcs	  = ducati_wkup_sleep_deps,
	.sleepdep_srcs	  = ducati_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain mpu_44xx_clkdm = {
	.name		  = "mpuss_clkdm",
	.pwrdm		  = { .name = "mpu_pwrdm" },
	.prcm_partition	  = OMAP4430_CM1_PARTITION,
	.cm_inst	  = OMAP4430_CM1_MPU_INST,
	.clkdm_offs	  = OMAP4430_CM1_MPU_MPU_CDOFFS,
	.wkdep_srcs	  = mpu_wkup_sleep_deps,
	.sleepdep_srcs	  = mpu_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain l3_2_44xx_clkdm = {
	.name		  = "l3_2_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_CORE_INST,
	.clkdm_offs	  = OMAP4430_CM2_CORE_L3_2_CDOFFS,
	.dep_bit	  = OMAP4430_L3_2_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP,
};

static struct clockdomain l3_1_44xx_clkdm = {
	.name		  = "l3_1_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_CORE_INST,
	.clkdm_offs	  = OMAP4430_CM2_CORE_L3_1_CDOFFS,
	.dep_bit	  = OMAP4430_L3_1_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP,
};

static struct clockdomain iss_44xx_clkdm = {
	.name		  = "iss_clkdm",
	.pwrdm		  = { .name = "cam_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_CAM_INST,
	.clkdm_offs	  = OMAP4430_CM2_CAM_CAM_CDOFFS,
	.wkdep_srcs	  = iss_wkup_sleep_deps,
	.sleepdep_srcs	  = iss_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_SWSUP,
};

static struct clockdomain l3_dss_44xx_clkdm = {
	.name		  = "l3_dss_clkdm",
	.pwrdm		  = { .name = "dss_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_DSS_INST,
	.clkdm_offs	  = OMAP4430_CM2_DSS_DSS_CDOFFS,
	.dep_bit	  = OMAP4430_DSS_STATDEP_SHIFT,
	.wkdep_srcs	  = l3_dss_wkup_sleep_deps,
	.sleepdep_srcs	  = l3_dss_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain l4_wkup_44xx_clkdm = {
	.name		  = "l4_wkup_clkdm",
	.pwrdm		  = { .name = "wkup_pwrdm" },
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.cm_inst	  = OMAP4430_PRM_WKUP_CM_INST,
	.clkdm_offs	  = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
	.dep_bit	  = OMAP4430_L4WKUP_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP | CLKDM_ACTIVE_WITH_MPU,
};

static struct clockdomain emu_sys_44xx_clkdm = {
	.name		  = "emu_sys_clkdm",
	.pwrdm		  = { .name = "emu_pwrdm" },
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.cm_inst	  = OMAP4430_PRM_EMU_CM_INST,
	.clkdm_offs	  = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
	.flags		  = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP |
			     CLKDM_MISSING_IDLE_REPORTING),
};

static struct clockdomain l3_dma_44xx_clkdm = {
	.name		  = "l3_dma_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_CORE_INST,
	.clkdm_offs	  = OMAP4430_CM2_CORE_SDMA_CDOFFS,
	.wkdep_srcs	  = l3_dma_wkup_sleep_deps,
	.sleepdep_srcs	  = l3_dma_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

/* As clockdomains are added or removed above, this list must also be changed */
static struct clockdomain *clockdomains_omap44xx[] __initdata = {
	&l4_cefuse_44xx_clkdm,
	&l4_cfg_44xx_clkdm,
	&tesla_44xx_clkdm,
	&l3_gfx_44xx_clkdm,
	&ivahd_44xx_clkdm,
	&l4_secure_44xx_clkdm,
	&l4_per_44xx_clkdm,
	&abe_44xx_clkdm,
	&l3_instr_44xx_clkdm,
	&l3_init_44xx_clkdm,
	&d2d_44xx_clkdm,
	&mpu0_44xx_clkdm,
	&mpu1_44xx_clkdm,
	&l3_emif_44xx_clkdm,
	&l4_ao_44xx_clkdm,
	&ducati_44xx_clkdm,
	&mpu_44xx_clkdm,
	&l3_2_44xx_clkdm,
	&l3_1_44xx_clkdm,
	&iss_44xx_clkdm,
	&l3_dss_44xx_clkdm,
	&l4_wkup_44xx_clkdm,
	&emu_sys_44xx_clkdm,
	&l3_dma_44xx_clkdm,
	NULL
};


void __init omap44xx_clockdomains_init(void)
{
	clkdm_register_platform_funcs(&omap4_clkdm_operations);
	clkdm_register_clkdms(clockdomains_omap44xx);
	clkdm_complete_init();
}