summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/amd/elba-asic-common.dtsi
blob: 46b6c6783f58a387110537bd5e304ab586eccec0 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
/*
 * Copyright 2020-2022 Advanced Micro Devices, Inc.
 */

&ahb_clk {
	clock-frequency = <400000000>;
};

&emmc_clk {
	clock-frequency = <200000000>;
};

&flash_clk {
	clock-frequency = <400000000>;
};

&ref_clk {
	clock-frequency = <156250000>;
};

&qspi {
	status = "okay";

	flash0: flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <40000000>;
		spi-rx-bus-width = <2>;
		m25p,fast-read;
		cdns,read-delay = <0>;
		cdns,tshsl-ns = <0>;
		cdns,tsd2d-ns = <0>;
		cdns,tchsh-ns = <0>;
		cdns,tslch-ns = <0>;
	};
};

&gpio0 {
	status = "okay";
};

&emmc {
	bus-width = <8>;
	cap-mmc-hw-reset;
	status = "okay";
};

&wdt0 {
	status = "okay";
};

&i2c0 {
	clock-frequency = <100000>;
	status = "okay";

	rtc@51 {
		compatible = "nxp,pcf85263";
		reg = <0x51>;
	};
};

&spi0 {
	#address-cells = <1>;
	#size-cells = <0>;
	num-cs = <4>;
	cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>,
		   <&porta 7 GPIO_ACTIVE_LOW>;
	status = "okay";
};