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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
*/
#include "amlogic-a4-common.dtsi"
#include "amlogic-a5-reset.h"
#include <dt-bindings/power/amlogic,a5-pwrc.h>
/ {
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
};
};
sm: secure-monitor {
compatible = "amlogic,meson-gxbb-sm";
pwrc: power-controller {
compatible = "amlogic,a5-pwrc";
#power-domain-cells = <1>;
};
};
};
&apb {
reset: reset-controller@2000 {
compatible = "amlogic,a5-reset",
"amlogic,meson-s4-reset";
reg = <0x0 0x2000 0x0 0x98>;
#reset-cells = <1>;
};
gpio_intc: interrupt-controller@4080 {
compatible = "amlogic,a5-gpio-intc",
"amlogic,meson-gpio-intc";
reg = <0x0 0x4080 0x0 0x20>;
interrupt-controller;
#interrupt-cells = <2>;
amlogic,channel-interrupts =
<10 11 12 13 14 15 16 17 18 19 20 21>;
};
};
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