summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
blob: 5ff64a0d2dcf8aeecd677b8215738184e5fe2348 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2016 Endless Computers, Inc.
 * Author: Carlo Caione <carlo@endlessm.com>
 */

#include "meson-gxl.dtsi"

/ {
	compatible = "amlogic,meson-gxm";

	cpus {
		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			clocks = <&scpi_dvfs 1>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x101>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			clocks = <&scpi_dvfs 1>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x102>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			clocks = <&scpi_dvfs 1>;
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x103>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			clocks = <&scpi_dvfs 1>;
		};
	};
};

&apb {
	usb2_phy2: phy@78040 {
		compatible = "amlogic,meson-gxl-usb2-phy";
		#phy-cells = <0>;
		reg = <0x0 0x78040 0x0 0x20>;
		clocks = <&clkc CLKID_USB>;
		clock-names = "phy";
		resets = <&reset RESET_USB_OTG>;
		reset-names = "phy";
		status = "okay";
	};

	mali: gpu@c0000 {
		compatible = "amlogic,meson-gxm-mali", "arm,mali-t820";
		reg = <0x0 0xc0000 0x0 0x40000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "job", "mmu", "gpu";
		clocks = <&clkc CLKID_MALI>;
		resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;

		/*
		 * Mali clocking is provided by two identical clock paths
		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
		 * free mux to safely change frequency while running.
		 */
		assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
				  <&clkc CLKID_MALI_0>,
				  <&clkc CLKID_MALI>; /* Glitch free mux */
		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
					 <0>, /* Do Nothing */
					 <&clkc CLKID_MALI_0>;
		assigned-clock-rates = <0>, /* Do Nothing */
				       <666666666>,
				       <0>; /* Do Nothing */
	};
};

&clkc_AO {
	compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
};

&saradc {
	compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
};

&scpi_dvfs {
	clock-indices = <0 1>;
	clock-output-names = "vbig", "vlittle";
};

&vpu {
	compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu";
};

&hdmi_tx {
	compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
};

&dwc3 {
	phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
};

&vdec {
	compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec";
};