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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
conn_subsys: bus@5b000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
conn_lpcg: clock-controller@5b200000 {
reg = <0x5b200000 0xb0000>;
#clock-cells = <1>;
};
usdhc1: mmc@5b010000 {
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>;
clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_0>;
status = "disabled";
};
usdhc2: mmc@5b020000 {
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b020000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>;
clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};
usdhc3: mmc@5b030000 {
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b030000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>;
clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_2>;
status = "disabled";
};
fec1: ethernet@5b040000 {
reg = <0x5b040000 0x10000>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_0>;
status = "disabled";
};
fec2: ethernet@5b050000 {
reg = <0x5b050000 0x10000>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_1>;
status = "disabled";
};
};
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