summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
blob: 840466e143b47d6635edb54b1643413401f9e481 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Marvell Armada AP807 Quad
 *
 * Copyright (C) 2019 Marvell Technology Group Ltd.
 */

#include "armada-ap807.dtsi"

/ {
	model = "Marvell Armada AP807 Quad";
	compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x000>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 0>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_0>;
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x001>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 0>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_0>;
		};
		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x100>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 1>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_1>;
		};
		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x101>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 1>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_1>;
		};

		l2_0: l2-cache0 {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <512>;
		};

		l2_1: l2-cache1 {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <512>;
		};
	};
};