path: root/arch/arm64/boot/dts/renesas/r9a09g057.dtsi

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/V2H(P) SoC
 *
 * Copyright (C) 2024 Renesas Electronics Corp.
 */

#include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "renesas,r9a09g057";
	#address-cells = <2>;
	#size-cells = <2>;

	audio_extal_clk: audio-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	/*
	 * The default cluster table is based on the assumption that the PLLCA55 clock
	 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
	 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
	 * clocked to 1.8GHz as well). The table below should be overridden in the board
	 * DTS based on the PLLCA55 clock frequency.
	 */
	cluster0_opp: opp-table-0 {
		compatible = "operating-points-v2";

		opp-1700000000 {
			opp-hz = /bits/ 64 <1700000000>;
			opp-microvolt = <900000>;
			clock-latency-ns = <300000>;
		};
		opp-850000000 {
			opp-hz = /bits/ 64 <850000000>;
			opp-microvolt = <800000>;
			clock-latency-ns = <300000>;
		};
		opp-425000000 {
			opp-hz = /bits/ 64 <425000000>;
			opp-microvolt = <800000>;
			clock-latency-ns = <300000>;
		};
		opp-212500000 {
			opp-hz = /bits/ 64 <212500000>;
			opp-microvolt = <800000>;
			clock-latency-ns = <300000>;
			opp-suspend;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			reg = <0>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>;
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu1: cpu@100 {
			compatible = "arm,cortex-a55";
			reg = <0x100>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>;
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu2: cpu@200 {
			compatible = "arm,cortex-a55";
			reg = <0x200>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>;
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu3: cpu@300 {
			compatible = "arm,cortex-a55";
			reg = <0x300>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>;
			operating-points-v2 = <&cluster0_opp>;
		};

		L3_CA55: cache-controller-0 {
			compatible = "cache";
			cache-unified;
			cache-size = <0x100000>;
			cache-level = <3>;
		};
	};

	gpu_opp_table: opp-table-1 {
		compatible = "operating-points-v2";

		opp-630000000 {
			opp-hz = /bits/ 64 <630000000>;
			opp-microvolt = <800000>;
		};

		opp-315000000 {
			opp-hz = /bits/ 64 <315000000>;
			opp-microvolt = <800000>;
		};

		opp-157500000 {
			opp-hz = /bits/ 64 <157500000>;
			opp-microvolt = <800000>;
		};

		opp-78750000 {
			opp-hz = /bits/ 64 <78750000>;
			opp-microvolt = <800000>;
		};

		opp-19687500 {
			opp-hz = /bits/ 64 <19687500>;
			opp-microvolt = <800000>;
		};
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	qextal_clk: qextal-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	rtxin_clk: rtxin-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	soc: soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		icu: interrupt-controller@10400000 {
			compatible = "renesas,r9a09g057-icu";
			reg = <0 0x10400000 0 0x10000>;
			#interrupt-cells = <2>;
			#address-cells = <0>;
			interrupt-controller;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "nmi",
					  "port_irq0", "port_irq1", "port_irq2",
					  "port_irq3", "port_irq4", "port_irq5",
					  "port_irq6", "port_irq7", "port_irq8",
					  "port_irq9", "port_irq10", "port_irq11",
					  "port_irq12", "port_irq13", "port_irq14",
					  "port_irq15",
					  "tint0", "tint1", "tint2", "tint3",
					  "tint4", "tint5", "tint6", "tint7",
					  "tint8", "tint9", "tint10", "tint11",
					  "tint12", "tint13", "tint14", "tint15",
					  "tint16", "tint17", "tint18", "tint19",
					  "tint20", "tint21", "tint22", "tint23",
					  "tint24", "tint25", "tint26", "tint27",
					  "tint28", "tint29", "tint30", "tint31",
					  "int-ca55-0", "int-ca55-1",
					  "int-ca55-2", "int-ca55-3",
					  "icu-error-ca55",
					  "gpt-u0-gtciada", "gpt-u0-gtciadb",
					  "gpt-u1-gtciada", "gpt-u1-gtciadb";
			clocks = <&cpg CPG_MOD 0x5>;
			power-domains = <&cpg>;
			resets = <&cpg 0x36>;
		};

		pinctrl: pinctrl@10410000 {
			compatible = "renesas,r9a09g057-pinctrl";
			reg = <0 0x10410000 0 0x10000>;
			clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 96>;
			#interrupt-cells = <2>;
			interrupt-controller;
			interrupt-parent = <&icu>;
			power-domains = <&cpg>;
			resets = <&cpg 0xa5>, <&cpg 0xa6>;
		};

		cpg: clock-controller@10420000 {
			compatible = "renesas,r9a09g057-cpg";
			reg = <0 0x10420000 0 0x10000>;
			clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
			clock-names = "audio_extal", "rtxin", "qextal";
			#clock-cells = <2>;
			#reset-cells = <1>;
			#power-domain-cells = <0>;
		};

		sys: system-controller@10430000 {
			compatible = "renesas,r9a09g057-sys";
			reg = <0 0x10430000 0 0x10000>;
			clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>;
			resets = <&cpg 0x30>;
		};

		ostm0: timer@11800000 {
			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
			reg = <0x0 0x11800000 0x0 0x1000>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD 0x43>;
			resets = <&cpg 0x6d>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ostm1: timer@11801000 {
			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
			reg = <0x0 0x11801000 0x0 0x1000>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD 0x44>;
			resets = <&cpg 0x6e>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ostm2: timer@14000000 {
			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
			reg = <0x0 0x14000000 0x0 0x1000>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD 0x45>;
			resets = <&cpg 0x6f>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ostm3: timer@14001000 {
			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
			reg = <0x0 0x14001000 0x0 0x1000>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD 0x46>;
			resets = <&cpg 0x70>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ostm4: timer@12c00000 {
			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
			reg = <0x0 0x12c00000 0x0 0x1000>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD 0x47>;
			resets = <&cpg 0x71>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ostm5: timer@12c01000 {
			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
			reg = <0x0 0x12c01000 0x0 0x1000>;
			interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD 0x48>;
			resets = <&cpg 0x72>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ostm6: timer@12c02000 {
			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
			reg = <0x0 0x12c02000 0x0 0x1000>;
			interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD 0x49>;
			resets = <&cpg 0x73>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ostm7: timer@12c03000 {
			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
			reg = <0x0 0x12c03000 0x0 0x1000>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD 0x4a>;
			resets = <&cpg 0x74>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		wdt0: watchdog@11c00400 {
			compatible = "renesas,r9a09g057-wdt";
			reg = <0 0x11c00400 0 0x400>;
			clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
			clock-names = "pclk", "oscclk";
			resets = <&cpg 0x75>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		wdt1: watchdog@14400000 {
			compatible = "renesas,r9a09g057-wdt";
			reg = <0 0x14400000 0 0x400>;
			clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
			clock-names = "pclk", "oscclk";
			resets = <&cpg 0x76>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		wdt2: watchdog@13000000 {
			compatible = "renesas,r9a09g057-wdt";
			reg = <0 0x13000000 0 0x400>;
			clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
			clock-names = "pclk", "oscclk";
			resets = <&cpg 0x77>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		wdt3: watchdog@13000400 {
			compatible = "renesas,r9a09g057-wdt";
			reg = <0 0x13000400 0 0x400>;
			clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
			clock-names = "pclk", "oscclk";
			resets = <&cpg 0x78>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		scif: serial@11c01400 {
			compatible = "renesas,scif-r9a09g057";
			reg = <0 0x11c01400 0 0x400>;
			interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eri", "rxi", "txi", "bri", "dri",
					  "tei", "tei-dri", "rxi-edge", "txi-edge";
			clocks = <&cpg CPG_MOD 0x8f>;
			clock-names = "fck";
			power-domains = <&cpg>;
			resets = <&cpg 0x95>;
			status = "disabled";
		};

		i2c0: i2c@14400400 {
			compatible = "renesas,riic-r9a09g057";
			reg = <0 0x14400400 0 0x400>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD 0x94>;
			resets = <&cpg 0x98>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@14400800 {
			compatible = "renesas,riic-r9a09g057";
			reg = <0 0x14400800 0 0x400>;
			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD 0x95>;
			resets = <&cpg 0x99>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@14400c00 {
			compatible = "renesas,riic-r9a09g057";
			reg = <0 0x14400c00 0 0x400>;
			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD 0x96>;
			resets = <&cpg 0x9a>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c3: i2c@14401000 {
			compatible = "renesas,riic-r9a09g057";
			reg = <0 0x14401000 0 0x400>;
			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD 0x97>;
			resets = <&cpg 0x9b>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c4: i2c@14401400 {
			compatible = "renesas,riic-r9a09g057";
			reg = <0 0x14401400 0 0x400>;
			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD 0x98>;
			resets = <&cpg 0x9c>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c5: i2c@14401800 {
			compatible = "renesas,riic-r9a09g057";
			reg = <0 0x14401800 0 0x400>;
			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD 0x99>;
			resets = <&cpg 0x9d>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c6: i2c@14401c00 {
			compatible = "renesas,riic-r9a09g057";
			reg = <0 0x14401c00 0 0x400>;
			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD 0x9a>;
			resets = <&cpg 0x9e>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c7: i2c@14402000 {
			compatible = "renesas,riic-r9a09g057";
			reg = <0 0x14402000 0 0x400>;
			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD 0x9b>;
			resets = <&cpg 0x9f>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c8: i2c@11c01000 {
			compatible = "renesas,riic-r9a09g057";
			reg = <0 0x11c01000 0 0x400>;
			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD 0x93>;
			resets = <&cpg 0xa0>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		gpu: gpu@14850000 {
			compatible = "renesas,r9a09g057-mali",
				     "arm,mali-bifrost";
			reg = <0x0 0x14850000 0x0 0x10000>;
			interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "job", "mmu", "gpu", "event";
			clocks = <&cpg CPG_MOD 0xf0>,
				 <&cpg CPG_MOD 0xf1>,
				 <&cpg CPG_MOD 0xf2>;
			clock-names = "gpu", "bus", "bus_ace";
			power-domains = <&cpg>;
			resets = <&cpg 0xdd>,
				 <&cpg 0xde>,
				 <&cpg 0xdf>;
			reset-names = "rst", "axi_rst", "ace_rst";
			operating-points-v2 = <&gpu_opp_table>;
			status = "disabled";
		};

		gic: interrupt-controller@14900000 {
			compatible = "arm,gic-v3";
			reg = <0x0 0x14900000 0 0x20000>,
			      <0x0 0x14940000 0 0x80000>;
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
		};

		sdhi0: mmc@15c00000  {
			compatible = "renesas,sdhi-r9a09g057";
			reg = <0x0 0x15c00000 0 0x10000>;
			interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>,
				 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>;
			clock-names = "core", "clkh", "cd", "aclk";
			resets = <&cpg 0xa7>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		sdhi1: mmc@15c10000 {
			compatible = "renesas,sdhi-r9a09g057";
			reg = <0x0 0x15c10000 0 0x10000>;
			interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>,
				 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>;
			clock-names = "core", "clkh", "cd", "aclk";
			resets = <&cpg 0xa8>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		sdhi2: mmc@15c20000 {
			compatible = "renesas,sdhi-r9a09g057";
			reg = <0x0 0x15c20000 0 0x10000>;
			interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>,
				 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>;
			clock-names = "core", "clkh", "cd", "aclk";
			resets = <&cpg 0xa9>;
			power-domains = <&cpg>;
			status = "disabled";
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
	};
};