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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3588-orangepi-5.dtsi"
/ {
model = "Xunlong Orange Pi 5 Max";
compatible = "xunlong,orangepi-5-max", "rockchip,rk3588";
vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
/* USB_OTG_PWREN */
gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_otg_pwren>;
regulator-name = "vcc5v0_usb30_otg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
};
&headphone_amp {
/* PHONE_CTL */
enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
};
&analog_sound {
pinctrl-names = "default";
pinctrl-0 = <&hp_detect>;
simple-audio-card,aux-devs = <&headphone_amp>;
simple-audio-card,hp-det-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
simple-audio-card,routing =
"Headphones", "LOUT1",
"Headphones", "ROUT1",
"LINPUT1", "Microphone Jack",
"RINPUT1", "Microphone Jack",
"LINPUT2", "Onboard Microphone",
"RINPUT2", "Onboard Microphone";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Microphone", "Onboard Microphone",
"Headphone", "Headphones";
};
&fan {
/* FAN_CTL_H */
pwms = <&pwm9 0 50000 0>;
};
&hym8563 {
interrupt-parent = <&gpio0>;
interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&rtc_int_l>;
};
&led_blue_pwm {
/* PWM_LED1 */
pwms = <&pwm4 0 25000 0>;
status = "okay";
};
&led_green_pwm {
/* PWM_LED2 */
pwms = <&pwm5 0 25000 0>;
};
/* phy2 */
&pcie2x1l1 {
reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie_eth>;
status = "okay";
};
&pinctrl {
hym8563 {
rtc_int_l: hym8563-int {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sound {
hp_detect: hp-detect {
rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
usb_host_pwren: usb-host-pwren {
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pwm4m0_pins>;
status = "okay";
};
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pwm5m1_pins>;
status = "okay";
};
&pwm9 {
pinctrl-names = "default";
pinctrl-0 = <&pwm9m2_pins>;
status = "okay";
};
&sfc {
pinctrl-names = "default";
pinctrl-0 = <&fspim2_pins>;
};
&u2phy0_otg {
phy-supply = <&vcc5v0_usb30_otg>;
};
&u2phy1_otg {
phy-supply = <&vcc5v0_usb20>;
};
&usb_host0_xhci {
dr_mode = "host";
};
/* pcie eth. not a real regulator. 33VAUX */
&vcc3v3_pcie_eth {
/* Ethernet_power_en */
gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
};
/*
* Represents the vcc5v0_usb20 and vcc5v0_usb30 in the schematic,
* both regulators share the same enable gpio
*/
&vcc5v0_usb20 {
/* USB_HOST_PWREN */
gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_host_pwren>;
};
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