1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
|
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
/*
* Copyright 2024 Mobileye Vision Technologies Ltd.
*/
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "img,i6500";
reg = <0>;
clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;
};
};
aliases {
serial0 = &uart0;
};
cpu_intc: interrupt-controller {
compatible = "mti,cpu-interrupt-controller";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
coherency-manager {
compatible = "mobileye,eyeq6-cm";
};
xtal: clock-30000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <30000000>;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
olb_acc: system-controller@d2003000 {
compatible = "mobileye,eyeq6h-acc-olb", "syscon";
reg = <0x0 0xd2003000 0x0 0x1000>;
#reset-cells = <1>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
olb_central: system-controller@d3100000 {
compatible = "mobileye,eyeq6h-central-olb", "syscon";
reg = <0x0 0xd3100000 0x0 0x1000>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
uart0: serial@d3331000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0 0xd3331000 0x0 0x1000>;
reg-io-width = <4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&olb_west EQ6HC_WEST_PER_UART>, <&olb_west EQ6HC_WEST_PER_OCC>;
clock-names = "uartclk", "apb_pclk";
};
pinctrl_west: pinctrl@d3337000 {
compatible = "pinctrl-single";
reg = <0x0 0xd3337000 0x0 0xb0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffff>;
};
olb_west: system-controller@d3338000 {
compatible = "mobileye,eyeq6h-west-olb", "syscon";
reg = <0x0 0xd3338000 0x0 0x1000>;
#reset-cells = <1>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
pinctrl_east: pinctrl@d3357000 {
compatible = "pinctrl-single";
reg = <0x0 0xd3357000 0x0 0xb0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffff>;
};
olb_east: system-controller@d3358000 {
compatible = "mobileye,eyeq6h-east-olb", "syscon";
reg = <0x0 0xd3358000 0x0 0x1000>;
#reset-cells = <1>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
olb_south: system-controller@d8013000 {
compatible = "mobileye,eyeq6h-south-olb", "syscon";
reg = <0x0 0xd8013000 0x0 0x1000>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
pinctrl_south: pinctrl@d8014000 {
compatible = "pinctrl-single";
reg = <0x0 0xd8014000 0x0 0xf8>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffff>;
};
olb_ddr0: system-controller@e4080000 {
compatible = "mobileye,eyeq6h-ddr0-olb", "syscon";
reg = <0x0 0xe4080000 0x0 0x1000>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
olb_ddr1: system-controller@e4081000 {
compatible = "mobileye,eyeq6h-ddr1-olb", "syscon";
reg = <0x0 0xe4081000 0x0 0x1000>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
gic: interrupt-controller@f0920000 {
compatible = "mti,gic";
reg = <0x0 0xf0920000 0x0 0x20000>;
interrupt-controller;
#interrupt-cells = <3>;
/*
* Declare the interrupt-parent even though the mti,gic
* binding doesn't require it, such that the kernel can
* figure out that cpu_intc is the root interrupt
* controller & should be probed first.
*/
interrupt-parent = <&cpu_intc>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;
};
};
};
};
#include "eyeq6h-pins.dtsi"
|
